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參數(shù)資料
| 型號： | TDC1020 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 10-Bit, 20 Msps High-Speed Monolithic A/D Converter(10位,20Msps 高速單片A/D轉(zhuǎn)換器) |
| 中文描述： | 10位，20 Msps的高速單片機的A / D轉(zhuǎn)換器（10位，20Msps高速單片的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 109K |
| 代理商： | TDC1020 |
TDC1020
PRODUCT SPECIFICATION
2
Functional Description
General Information
The TDC1020 is a flash analog-to-digital (A/D) converter in
which each of the 1024 comparators has one input biased at
one of the transition points of the transfer function and all of
the other comparator inputs are connected to the analog input
signal. The output of the comparator array is sometimes
referred to as a “thermometer” code as all of comparators
biased at voltages more positive than the input voltage will
be off and the rest will be on. The thermometer code from
the comparator array is encoded into an 11-bit code (10 data
bits plus an overflow bit). The format of the code that is
encoded is determined by the format controls NMINV and
NLINV so that the data presented to the output latches is in
binary, two’s complement or inverted data format.
Power and Thermal Management
The TDC1020 operates from two supply voltages, +5.0V
and -5.2V. The bulk of the current drawn by the positive
supply is returned through the negative supply, however,
the positive supply should be referenced to digital ground
(D
GND
) and the negative supply to analog ground (A
All power and ground pins must be connected. The maxi-
mum power is drawn at the lower limit of the operating
temperature range. When the device is being operated at
elevated temperatures, the power dissipation drops, however,
thermal management will then be a consideration. The
TDC1020 is rated for operation in a 70
temperature in still air.
GND
).
°
C ambient
The power dissipation decreases with increasing tempera-
ture. Fairchild specifies the absolute maximum I
specifications in the Electrical Characteristics Table.
The worst case conditions are V
and the case temperature equal to 0
of 0
°
C is, however, a transient condition since the device
immediately warms up and decreases its power dissipation,
upon power up. For typical steady state power dissipation as
a function of ambient temperature, please see Figure 7.
EE
and I
CC
CC
= 5.25V, V
°
C. The case temperature
EE
= -5.5V
It is possible to relax the temperature requirements of the
device by providing adequate heat sinking.
Reference
The bias voltages for the comparator array are provided by
use of a serial chain of 1024 equal-valued resistors across
which the reference voltage is applied. Seven equally
separated mid-point adjustment taps are provided to allow
the user to optimize the integral linearity of the device. In
addition, there are sense leads on the top and bottom of the
resistor chain which allow the user to minimize the offset
and gain errors of the device. It is recommended that the user
drive R
M2
, R
M4
and R
M6
in order to obtain optimal device
performance. One method for driving the references is
shown in Figure 7. The reference top and reference bottom
sources must be able to source or sink the reference current
and since noise on these leads will lead to inaccurate conver-
sions, they should be bypassed with a capacitor to A
There are in addition 4 more reference taps, the use of which
is not required to obtain 0.1 % integral linearity. It is recom-
mended that these pins be left open (no connection).
GND
.
Format Control
There are two inputs provided on the TDC1020 which
control the output format of the device. When NMINV is
connected to a logic LOW, the MSB is inverted. When
NLINV is connected to a logic LOW D
inverted. By using various combinations of these commands
the user can select any of the following output data formats:
binary, inverted binary, two’s complement, inverted two’s
complement. The Output Coding Table shows the output
formats generated for each of the control states.
2
through D
10
will be
Convert
The analog input to the TDC1020 is sampled at a time t
after the rising edge of the CONV signal. The output data
from the 1024 comparators is encoded into the proper format
and the final result is transferred to the output latches on
the next rising edge. This timing is shown in the Timing
Diagram (Figure 1). Note that there are minimum LOW
and HIGH requirements of the CONV signal (t
which must be met for proper device operation. In addition,
the performance is generally improved if the CONV signal is
LOW for as long as possible. A circuit which provides an
optimized waveshape CONV signal to the TDC1020 is
shown on Figure 7.
STO
PWH
, t
PWL
)
Analog Input
The analog input to the TDC1020 has an equivalent circuit
shown in Figure 2. It should be noted that the major compo-
nent of the input impedance is capacitance, and the input
range is 4Vp-p. A low-impedance driving circuit is recom-
mended for the TDC1020 to obtain good dynamic perfor-
mance. All analog inputs to the TDC1020 must be connected
to insure proper operation of the A/D converter.
Outputs
The data and overflow outputs of the TDC1020 are TTL
compatible, capable of driving four low power Schottky TTL
(54/74 LS) unit loads. The outputs hold the previous data a
minimum time t
HO
after the rising edge of the CONV signal.
New data becomes valid after a maximum delay time. t
D
.
No Connects
There are several pins labelled No Connect (NC) which have
no electrical connection to the chip. These pins should be
connected to AGND for best noise performance.
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