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參數資料
| 型號： | TDC1020 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 10-Bit, 20 Msps High-Speed Monolithic A/D Converter(10位,20Msps 高速單片A/D轉換器) |
| 中文描述： | 10位，20 Msps的高速單片機的A / D轉換器（10位，20Msps高速單片的A / D轉換器） |
| 文件頁數： | 10/16頁 |
| 文件大?。?/td> | 109K |
| 代理商： | TDC1020 |
TDC1020
PRODUCT SPECIFICATION
10
Applications Discussion
Calibration
Calibration of the TDC1020 consists of adjusting the refer-
ence taps so that the converters integral linearity, gain and
offset errors are minimized. To minimize the offset errors the
sense leads must be used properly. The sense leads are not
designed to carry very much current (<1mA) and should
therefore be used in a feedback loop to a high-impedance
input such as that shown in Figure 7. When a circuit similar
to that in Figure 7 is used for generating the reference volt-
ages, calibration can be achieved with the following proce-
dure:
1.
Apply an input to the input amplifier which is 1/2 LSB
less than full-scale (A/D input = 1.998V) and adjust the
gain so that the output of the A/D is toggling between
full-scale and one LSB below full-scale (11111111111
and 1111111110 for binary conversions).
2.
Apply an input to the input amplifier which is 1/2 LSB
greater than zero-scale (A/D input = 1.998V) and adjust
V
RB
via the V
RG
pot so that the output of the A/D is
toggling between 0 and 1 (0000000000 and 0000000001
for binary conversions).
The A/D converter will now be calibrated to provide accurate
conversions throughout its input range. To optimize the
integral linearity of the device set up the “Subtractive Ramp
Test” described in the TRW Applications Note TP-30,
Understanding Flash A/D Converter Terminology
, then
adjust the mid-point taps to minimize the bow in the error
curve.
Typical Interface
A Typical Interface Circuit is shown of the TDC1020 in Fig-
ure 7. The analog input amplifier, a THC4231, is used to
directly drive the A/D converter. This amplifier is set up to
have a gain of four and will provide the recommended +2 to
-2V input signal to the TDC1020 when it has a 1Vp-p input
signal. All four analog input pins are connected in parallel to
decrease the parasitic inductance. An LM313 is used to
provide a stable reference voltage which is buffered by a
dual op-amp, generating V
RT
and V
RB
. Both op-amps have
their outputs buffered by an emitter follower to decrease the
output impedance seen by the reference resistor chain. To
minimize noise coupling into the reference resistor chain,
bypass capacitors have been added, bypassing the reference
taps to ground.
Since capacitive coupling from the digital signals to the
analog input will adversely affect the converter performance,
careful attention to board layout is recommended.
As is true with most bipolar integrated circuits, the substrate
of the TDC1020 (V
EE
); must be the most negative potential
applied. This rule applies for all conditions of temperature,
signal level and power supply sequencing. In many systems,
the voltage reference generators and input driving amplifier
are powered from voltages greater than the +5 and -5.2V of
the TDC1020. Whenever this situation occurs, it is always
possible for the V
EE
inputs of the TDC1020 to be positive
with respect to the V
IN
or V
RG
inputs when power supplies
are cycled ON and OFF.
To protect the TDC1020 from latch-up due to substrate bias,
Fairchild recommends the use of a lN5818 Schottky diode
connected between VEE and VIN and another between
V
EE
and V
RG
with the anode of each diode connected to
V
EE
. The diodes prevent V
IN
and V
RT
from going more than
0.4V more negative than V
EE
. This protection circuit is
shown in Figure 7.
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