參數(shù)資料
型號(hào)： TDA9875A
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Digital TV Sound Processor DTVSP
中文描述： SPECIALTY CONSUMER CIRCUIT, PDIP64
封裝： SHRINK, PLASTIC, DIP
文件頁(yè)數(shù)： 34/96頁(yè)
文件大小： 296K
代理商： TDA9875A
1999 Dec 20
34
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
The following sub-sections provide a detailed description of the slave receiver registers.
10.3.1
AGC
GAIN REGISTER
If the automatic gain control function is switched off in the general configuration register, the contents of this register will
define a fixed gain of the AGC stage. The input voltages given are meant to generate a full-scale output from the SIF
ADC. If automatic gain control is on, the AGCGAIN setting is ignored. After switching off the automatic gain control
function, the latest gain control setting is copied to the AGC gain register.
If the AGC input level shift bit AGCLEV is set to logic 1 the input signal is scaled with
10 dB. The AGCLEV bit is also
active if the automatic gain function is enabled.
It should be noted that the input voltages should be considered as approximate target values.
Table 14
Subaddress 0 (note 1)
Note
1.
The default setting at power-up is 0000 0000.
38
39
40
41
42
43
44
45
0
0
0
0
0
0
0
b
0
0
m
0
0
0
0
b
0
0
m
0
0
0
v
b
i
i
i
i
i
I
2
S1 input level adjust
I
2
S1 output level adjust
I
2
S2 output select
I
2
S2 input level adjust
I
2
S2 output level adjust
beeper frequency
beeper volume, Main and Auxiliary
bass boost, Main left and right
o
m
i
o
0
v
b
o
0
i
o
0
v
b
o
s
i
o
f
v
b
o
s
i
o
f
v
b
o
s
i
o
f
v
b
BIT
NAME
VALUE
DESCRIPTION
7 (MSB)
6
5
B7
B6
0
0
1
0
set to logic 0
set to logic 0
input signal scaled with
10 dB
input signal not scaled
gain control bits (see Table 15)
AGCLEV
4
3
2
1
AGCGAIN
0 (LSB)
SUBADDRESS
(DECIMAL)
DATA
FUNCTION
MSB
LSB
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