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參數(shù)資料
| 型號： | TDA9852 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | I2C-bus controlled BTSC stereo/SAP decoder and audio processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP42 |
| 文件頁數(shù)： | 10/40頁 |
| 文件大?。?/td> | 258K |
| 代理商： | TDA9852 |
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1997 Mar 11
10
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
M
UTE
The mute function can be activated independently with last
step of volume control at the left or right output. By setting
the general mute bit GMU via the I
2
C-bus all outputs are
muted. All channels include an independent zero cross
detector. The zero crossing mute feature can be selected
via bit TZCM:
TZCM = 0: forced mute with direct execution
TZCM = 1: execution in time with signal zero crossing.
In the zero cross mode a change in the GMU polarity is
activated but not executed. The execution is enabled at
the next zero crossing of the signal. To avoid a large delay
of mute switching, when very low frequencies are
processed, or the output signal amplitude is lower than the
DC offset voltage, the following I
2
C-bus transmissions are
needed:
a first transmission for mute execution
a second transmission about 100 ms later, which must
switch the zero crossing mode to forced mute
(TZCM = 0)
a third transmission to reactivate the zero crossing
mode (TZCM = 1). This transmission can take place
immediately, but must follow before the next mute
execution.
Adjustment procedure
C
OMPOSITE INPUT LEVEL ADJUSTMENT
Feed in from FM demodulator the composite signal with
100% modulation (25 kHz deviation) L + R; f
i
= 300 Hz.
Set input level control via I
2
C-bus monitoring line out
(500 mV
±
20 mV). Store the setting in a non-volatile
memory.
A
UTOMATIC ADJUSTMENT PROCEDURE
Capacitors of external inputs LIL and LIR must be
grounded at EIL and EIR
Composite input signal L = 300 Hz, R = 3.1 kHz,
14% modulation for each channel; volume gain +16 dB
via I
2
C-bus
Effects, AVL, loudness
off
.
Line out setting bits: STEREO = 1, SAP = 0
(see Table 12)
Selector setting SC0, SC1, SC2 = 0, 0, 0 (see Table 11)
Start adjustment by transmission ADJ = 1 in register
ALI3; the decoder will align itself
After 1 second minimum stop alignment by transmitting
ADJ = 0 in register ALI3 read the alignment data by an
I
2
C-bus read operation from ALR1 and ALR2
(see Chapter “I
2
C-bus protocol”) and store it in a
non-volatile memory; the alignment procedure
overwrites the previous data stored in ALI1 and ALI2
Disconnect the capacitors of external inputs from
ground.
M
ANUAL ADJUSTMENT
Manual adjustment is necessary when no dual tone
generator is available (e.g. for service).
Spectral and wideband data have to be set to 10000
(middle position for adjustment range)
Composite input L = 300 Hz; 14% modulation
Adjust channel separation by varying wideband data
Composite input L = 3 kHz; 14% modulation
Adjust channel separation by varying spectral data
Iterative spectral/wideband operation for optimum
adjustment
Store data in non-volatile memory.
T
IMING CURRENT FOR RELEASE RATE
Due to possible internal and external spreading, the timing
current can be adjusted via I
2
C-bus, see Table 20, as
recommended by dbx.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA9852H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled BTSC stereo/SAP decoder and audio processor |
| TDA9852H/V2,557 | 功能描述:音頻放大器 TDA9852H/QFP44/TRAYDPM//V2 RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
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| TDA9853H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled economic BTSC stereo decoder and audio processor |
| TDA9853HV1 | 制造商:PHILIPS 功能描述:New |
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