- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383990 > TDA9332 (NXP Semiconductors N.V.) I2C-bus controlled TV display processors PDF資料下載
參數(shù)資料
| 型號： | TDA9332 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | I2C-bus controlled TV display processors |
| 中文描述： | 的I2C控制的電視顯示處理器總線 |
| 文件頁數(shù)： | 14/56頁 |
| 文件大?。?/td> | 228K |
| 代理商： | TDA9332 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
2000 May 08
14
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled TV display processors
TDA933xH series
Table 27
Long blanking mode
Table 28
Vertical free-running frequency in TV mode
Table 29
De-interlace phase
Table 30
Switch-off in vertical overscan
Table 31
Select vertical frequency
Table 32
Enable vertical guard (RGB blanking)
Table 33
Interlace
Table 34
Soft clipping level
Table 35
Clamp pulse timing
Note
1.
See Chapter “Characteristics”; note 13.
Table 36
Start line blanking (15 steps; 2 line locked clock
period per step; 1 line period is 440 LLC pulses)
Note
1.
See Chapter “Characteristics”; note 13.
Output status bits
Table 37
Power-on reset
Table 38
Field frequency indication
Table 39
Phase 1 (
1
) lock indication
LBM
BLANKING MODE
0
1
adapted to standard (50 or 60 Hz)
fixed in accordance with 50 Hz standard
VFF
FREQUENCY
0
1
50 Hz (SVF = 0) or 100 Hz (SVF = 1)
60 Hz (SVF = 0) or 120 Hz (SVF = 1)
DIP
PHASE
0
delay of 1st field (start of synchronized V
D
pulse coincides with H-flyback) with 0.5 H
delay of 2nd field with 0.5 H
1
OSO
MODE
0
1
switch-off undefined
switch-off in vertical overscan
SVF
MODE
0
1
vertical frequency is 50 or 60 Hz
vertical frequency is 100 or 120 Hz
EVG
VERTICAL GUARD MODE
0
1
not active
active
DL
STATUS
0
1
interlace
de-interlace
SC1
SC0
VOLTAGE DIFFERENCE
BETWEEN SOFT CLIPPING AND
PWL
0
0
1
1
0
1
0
1
0% above PWL
5% above PWL
10% above PWL
soft clipping off
HDCL
MODE
(1)
0
1
normal timing
HDTV timing
LBL3
LBL2
LBL1
LBL0
START LINE
BLANKING
(1)
0
0
1
0
1
1
0
1
1
0
1
1
+14 LLC
normal
16 LLC
POR
MODE
0
1
normal
power-down
FSI
FREQUENCY
0
1
50 or 100 Hz
60 or 120 Hz
SL
INDICATION
0
1
not locked
locked
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TDA9332H | I2C-bus controlled TV display processors |
| TDA9850 | I2C-bus controlled BTSC stereo/SAP decoder |
| TDA9850T | I2C-bus controlled BTSC stereo/SAP decoder |
| TDA9851 | I2C-bus controlled economic BTSC stereo decoder |
| TDA9851T | I2C-bus controlled economic BTSC stereo decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA9332H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled TV display processors |
| TDA9380 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TDA938O超級芯片將微處理器(CPU)與TV信號處理器集成在一起 |
| TDA9383 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| TDA9400 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:INTEGRATED CIRCUITS FOR TV AND RADIO RECEVERS |
| TDA9403 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:INTEGRATED CIRCUITS FOR TV AND RADIO RECEVERS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。