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參數(shù)資料
| 型號： | TDA9321H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | I2C-bus controlled TV input processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 31/44頁 |
| 文件大小： | 249K |
| 代理商： | TDA9321H |
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1998 Dec 16
31
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled TV input processor
TDA9321H
Notes to the characteristics
1.
The two supply pins V
P1
and V
P2
must be decoupled separately but they must be connected to a single power supply
to avoid too big differences between them.
2.
On set AGC.
3.
This parameter is not tested during production and is just given as application information for the designer of the
television receiver.
4.
Loop filter bandwidth B
lpf
= 60 kHz (natural frequency f
n
= 15 kHz; damping factor d = 2; calculated with top sync
level as f
PLL
input signal level). LC-VCO circuit between pins 7 and 8: Q
0
= 60; C
int
= 30 pF.
5.
The optimum temperature stability of the PLL can be obtained when a TOKO coil as given in Table 55 is applied.
6.
This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.
7.
Measured at 10 mV (RMS value) top sync input signal.
8.
So called projected zero point, i.e. with switched demodulator.
9.
Measured in accordance with the test line given in Fig.5. For the differential phase test the peak white setting is
reduced to 87%.
The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and
smallest value relative to the subcarrier amplitude at blanking level.
The differential phase is defined as the difference in degrees between the largest and smallest phase angle.
10. This figure is valid for the complete video signal amplitude (peak white-to-black). See Fig.6.
11. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal).
t
d
delay between mid sync of input
and start of clamping pulse
note 30
3.0
3.2
3.4
μ
s
I
2
C-BUS CONTROL
SCL
AND
SDA
INPUTS
/
OUTPUTS
(
PINS
SCL
AND
SDA)
V
i
V
IL
V
IH
I
IL
I
IH
V
OL(SDA)
input voltage range
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
LOW-level output voltage on
pin SDA
0
3.5
5.5
1.5
10
10
0.4
V
V
V
μ
A
μ
A
V
V
IL
= 0 V
V
IH
= 5.5 V
I
OL(SDA)
= 3 mA
SW0
AND
SW1
OUTPUTS
(
PINS
SW0
AND
SW1); note 36
V
OH
V
OL
I
O(sink)
I
O(source)
HIGH-level output voltage
LOW-level output voltage
output sink current
output source current
4.0
2
2
5.0
0.2
5.5
0.4
V
V
mA
mA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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