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參數(shù)資料
| 型號(hào)： | TDA9321H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | I2C-bus controlled TV input processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 18/44頁(yè) |
| 文件大?。?/td> | 249K |
| 代理商： | TDA9321H |
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1998 Dec 16
18
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled TV input processor
TDA9321H
CHARACTERISTICS
V
P
= 8 V; T
amb
= 25
°
C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply (pins V
P1
and V
P2
);
note 1
V
P
supply voltage
(pins V
P1
and V
P2
)
supply current
(pins V
P1
and V
P2
)
total power dissipation
7.2
8.0
8.8
V
I
P
120
140
mA
P
tot
960
mW
Vision IF circuit
V
ISION
IF
AMPLIFIER INPUTS
(
PINS
VIF1
AND
VIF2)
V
i(rms)
input sensitivity (RMS value)
note 2
f
i(VIF)
= 38.90 MHz
f
i(VIF)
= 45.75 MHz
f
i(VIF)
= 58.75 MHz
150
35
35
40
200
100
100
100
μ
V
μ
V
μ
V
mV
V
i(max)(rms)
maximum input signal
(RMS value)
differential input resistance
differential input capacitance
voltage gain control range
R
i(dif)
C
i(dif)
G
v
PLL
DEMODULATOR
(PLL
FILTER ON PIN
VIFPLL); note 4
note 3
note 3
70
2
3
75
80
k
pF
dB
f
PLL
f
cr(PLL)
t
acq(PLL)
f
VCO
/
T
PLL frequency range
PLL catching range
PLL acquisition time
VCO frequency dependency
with temperature
VCO tuning frequency range
frequency variation per step of
the DAC (A0 to A6)
frequency shift
32
2.0
2.7
60
3.3
20
±
20
×
10
6
K
1
MHz
MHz
ms
notes 5 and 6
f
tune(VCO)
f
DAC
via I
2
C-bus
3.0
23
3.7
29
4.2
33
MHz
kHz
f
shift
V
IDEO AMPLIFIER OUTPUT
(
PIN
VIFO); note 7
with bit L’FA
5.5
MHz
V
o(z)
zero signal output level
note 8
negative modulation
positive modulation
negative modulation
positive modulation
4.6
1.9
1.9
4.4
4.7
2.0
2.0
4.5
0
4.8
2.1
2.1
4.6
15
V
V
V
V
%
V
o(ts)
V
o(w)
V
o
top-sync level
white level
difference in amplitude
between negative and positive
modulation
video output impedance
internal bias current of NPN
emitter follower output transistor
Z
o(v)
I
bias(int)
1.0
50
mA
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