參數(shù)資料
型號(hào): TDA9321
廠商: NXP Semiconductors N.V.
英文描述: I2C-bus controlled TV input processor
中文描述: 的I2C控制的電視處理器總線輸入
文件頁數(shù): 28/44頁
文件大?。?/td> 249K
代理商: TDA9321
1998 Dec 16
28
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled TV input processor
TDA9321H
Z
o
V
O
B
RGB(
3dB)
output impedance
output DC voltage level
3 dB bandwidth of the RGB
switch circuit
signal-to-noise ratio
black set-up amplitude
2.8
7
3.0
250
3.2
V
MHz
black level
S/N
V
su(bl)
f
i
= 0 to 5 MHz
bit MACP = 1 or
bit HD = 1
190
52
200
210
dB
mV
t
W(su)(bl)
t
d
black set-up pulse width
delay between mid sync at input
and black set-up
offset voltage
gain from internal Y/CVBS
to YO
52.8
8.8
μ
s
μ
s
note 30
V
offset
G
(Y/CVBS-YO)
Y
bl
to re-inserted black
1.35
1.08
1.43
1.14
10
1.50
1.20
mV
bit MACP = 1 or
bit HD = 1
UO
AND
VO
SIGNAL OUTPUTS
(
PINS
UO
AND
VO)
V
o(VO)(p-p)
output voltage on pin VO
(peak-to-peak value)
output voltage on pin UO
(peak-to-peak value)
output impedance
output DC voltage level
difference in black level
between YUV and RGB mode
standard EBU colour bar
0.88
1.05
1.25
V
V
o(UO)(p-p)
standard EBU colour bar
1.12
1.33
1.58
V
Z
o
V
O
V
bl(YUV-RGB)
2.2
2.4
250
2.6
10
V
mV
C
OLOUR
M
ATRIX FROM
RGB
TO
YUV
G
gain
from RI to YO
from GI to YO
from BI to YO
from RI to UO
from GI to UO
from BI to UO
from RI to VO
from GI to VO
from BI to VO
0.40
0.79
0.15
0.40
0.79
1.19
0.94
0.79
0.15
0.43
0.84
0.16
0.43
0.84
1.27
1.00
0.84
0.16
0.46
0.90
0.17
0.46
0.90
1.35
1.07
0.90
0.17
Horizontal and vertical synchronization
S
YNC VIDEO INPUTS
V
sync
SL
hor
SL
vert
sync pulse amplitude
slicing level for horizontal sync
slicing level for vertical sync
note 3
note 32
note 32
35
50
35
300
55
40
350
60
45
mV
%
%
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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