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參數(shù)資料
| 型號： | TDA9321 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | I2C-bus controlled TV input processor |
| 中文描述： | 的I2C控制的電視處理器總線輸入 |
| 文件頁數(shù)： | 12/44頁 |
| 文件大?。?/td> | 249K |
| 代理商： | TDA9321 |
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1998 Dec 16
12
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled TV input processor
TDA9321H
Table 5
Motion Adaptive Colour Plus (MACP)
Note
1.
The black set-up will only be present in a norm sync
condition.
Table 6
Helper output blanking (PALplus/EDTV-2)
Note
1.
X = don’t care.
Table 7
PALplus helper demodulation active
Note
1.
Black and helper set-up will only be present in a norm
sync condition.
Table 8
Forced colour on
Table 9
Automatic colour limiting
MACP
MODE
0
1
internal 4.43 MHz trap used
external MACP chrominance filtering used;
4.43 MHz trap bypassed and black set-up
200 mV; note 1
HOB
HBC
X
(1)
0
1
1
SNR
X
(1)
X
(1)
0
1
BLANKING
0
1
1
1
off
on
off
on
HD
CONDITIONS
0
1
off
on; PALplus mode with helper set-up 400 mV
and black set-up 200 mV; note 1
FCO
MODE
0
1
not active
active
ACL
COLOUR LIMITING
0
1
not active
active
Table 10
Chrominance band-pass centre frequency
Table 11
Bypass of chrominance baseband delay line
Table 12
Gain luminance channel
Table 13
Y-delay adjustment; note 1
Note
1.
For an equal delay of the luminance and chrominance
signal the delay must be set at a value of 280 ns
(YD3 to YD0 = 1011). This is only valid for a CVBS
signal without group delay distortions.
Table 14
Forced field frequency
Note
1.
When switched to this mode the divider will directly
switch to forced 60 Hz only.
CB
CENTRE FREQUENCY
0
1
f
c
1.1
×
f
c
BPS
DELAY LINE MODE
0
1
active
bypassed
GAI1
GAI0
GAIN SETTING
0
0
1
1
0
1
0
1
1 dB
0 dB
+1 dB
+2 dB
YD0 to YD3
Y-DELAY
YD3
YD2
YD1
YD0
YD3
×
160 ns +
YD2
×
160 ns +
YD1
×
80 ns +
YD0
×
40 ns
FORF
FORS
FIELD FREQUENCY
0
0
auto (60 Hz when line not
synchronized)
forced 60 Hz; note 1
keep last detected field frequency
auto (50 Hz when line not
synchronized)
0
1
1
1
0
1
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| TDA9321H | I2C-bus controlled TV input processor |
| TDA9330 | I2C-bus controlled TV display processors |
| TDA9330H | I2C-bus controlled TV display processors |
| TDA9331H | I2C-bus controlled TV display processors |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA9321H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled TV input processor |
| TDA9330 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled TV display processors |
| TDA9330H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled TV display processors |
| TDA9331H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled TV display processors |
| TDA9332 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled TV display processors |
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