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參數(shù)資料
| 型號(hào)： | TDA9209 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP24 |
| 封裝： | PLASTIC, SHRINK, DIP-24 |
| 文件頁(yè)數(shù)： | 22/22頁(yè) |
| 文件大?。?/td> | 1670K |
| 代理商： | TDA9209 |
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TDA9209
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4.12 Stand-by Mode
The TDA9209 has a stand-by mode. As soon as
the VCC power (Pin 20) gets lower than 3V (typ.),
the device is set in stand-by mode whatever the
voltage on analog VCCA (Pin 7) is. The analog
blocks are internally switched-off while the logic
parts (I2C bus, power-on reset) are still supplied.
In stand-by mode, the power consumption is be-
low 20 mW.
4.13 Serial Interface
The 2-wire serial interface is an I2C interface. The
slave address of TDA9209 is DC hex.
The host MCU can write into the TDA9209 regis-
ters. Read mode is not available.
In order to write data into the TDA9209, after the
“start” message, the MCU must send the following
data (see Figure 8):
– the I2C address slave byte with a low level for the
R/W bit,
– the byte to the internal register address where
the MCU wants to write data,
– the data.
All bytes are sent with MSB bit first. The transfer of
written data is ended with a “stop” message.
When transmitting several data, the register ad-
dresses and data can be written with no need to
repeat the start and slave addresses.
4.14 Power-on Reset
A power-on reset function is implemented on the
TDA9209 so that the I2C registers have a deter-
mined status after power-on. The Power-on reset
threshold for a rising supply on VCCA (Pin 7) is
3.8 V (typ.) and 3.2V when the VCC decreases.
Figure 8. I2C Write Operation
4.15 Video detection (see Figure 9)
The video detection consists of three fast compa-
rators and a OR function.
The positive input of each comparator is connect-
ed to the input video pin (R, G, or B).
The negative inputs are connected together to a
reference voltage. This voltage is the threshold of
the comparators. The typical threshold voltage is
120 mV. The three comparator outputs are con-
nected to the OR inputs. Active Video output can
be inhibited by using bit 7 in Register 13 :
When AV output is validated, the AV output reach-
es 5V when at least one of the 3 video inputs gets
higher than 3.8V (typ.), and decreases to 0V if the
3 input voltages get lower than 3.2V (typ.).
Figure 9. Video Detection
A6
A5
A4
A3
A2
A1
A0
W
11
01110
0
SCL
W
A7
A6
A5
A4
A3
A2
A1
A0
SDA
Register Address
ACK
I2C Slave Address
Start
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte
ACK
Stop
R13b7 = 0
AV inhibited
R13b7 = 1
AV validated
120mV
R13b7=0
AV
IN1
IN2
IN3
8
1
3
5
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