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參數(shù)資料
| 型號(hào)： | TDA9209 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP24 |
| 封裝： | PLASTIC, SHRINK, DIP-24 |
| 文件頁(yè)數(shù)： | 18/22頁(yè) |
| 文件大?。?/td> | 1670K |
| 代理商： | TDA9209 |
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TDA9209
5/22
4.5 Brightness Adjustment (8 bit)
Brightness adjustment is controlled by the I2C Bus
via Register 2. It consists of adding the same DC
voltage to the three RGB signals, after contrast ad-
justment. When the blanking pulse equals 0, the
DC voltage is set to a value which can be adjusted
between 0 and 2V with 8mV steps (see Figure 3).
The DC output level is forced to the "Infra Black"
level (VDC) when the blanking pulse is equal to 1.
4.6 Drive Adjustment (3 x 8 bit)
In order to adjust the white balance, the TDA9209
offers the possibility of adjusting separately the
overall gain of each channel thanks to the I2C bus
(Registers 3, 4 and 5).
The very large drive adjustment range (48 dB) al-
lows different standards or custom color tempera-
tures.
It can also be used to adjust the output voltages at
the optimum amplitude to drive the CRT drivers,
keeping the whole contrast control for the end-
user only.
The drive adjustment is located after the Contrast,
Brightness and OSD switch blocks, so it does not
affect the white balance setting when the BRT is
adjusted. It also operates on the OSD portion of
the signal.
4.7 Cut-off Adjustment (Infra Black)
The cut-off voltage (Infra Black:VDC) is the level of
the output during the blanking period. This level is
sampled after each line during an internal pulse
(OCL) generated during the blanking pulse (see
Figure 11).
A sample-and-hold block controls the VDC level.
In case of AC coupling application, VDC is adjusta-
ble simultaneously on the 3 channels from 0.4 to
2.5V via the 4-bit DCL register (register 6, see
Table 1 on page 15).
In case of DC coupling, VDC is adjustable sepa-
rately for each channel from 0.2 to 2.5V via the
8-bit cut-off registers (registers 10, 11 and 12, see
Table 1 on page 15).
Caution:
Register 6: out of the 0 to 15 cut-off adjustment
steps, the first 3 steps are not allowed.
Registers 10, 11 and 12: out of the 0 to 256 cut-off
adjustment steps, the first 40 steps are not al-
lowed.
4.8 OSD Inputs
The TDA9209 allows to mix the OSD signals into
the RGB main picture. The four pins dedicated to
this function are the following:
– Three TTL RGB inputs (Pins 9, 10, 11) connect-
ed to the three outputs of the corresponding OSD
processor.
– One TTL fast blanking input (Pin 12) also con-
nected to the FBLK output of the OSD processor.
When a high level is present on the FBLK, the IC
acts as follows:
– The three main picture RGB input signals (IN1,
IN2, IN3) are internally switched to the internal
input clamp reference voltage.
– The three output signals are set to the voltage
corresponding to the three OSD input logic
states (0 or 1). (See Figure 3).
If the OSD input is at low level, the output and
brightness voltages (VBRT) are equal.
If the OSD input is at high level, the output voltage
is VOSD, where VOSD = VBRT + OSD and OSD is
an I2C bus-controlled voltage.
OSD varies between 0 V to 4.9 V by 320 mV steps
via Register 7 (4 bit). The same variation is applied
simultaneously to the three channels providing the
OSD contrast.
The grey color can be obtained on output signals
when:
– OSD1 = 1, OSD2 = 0 and OSD3 = 1,
– A special bit (bit 5 or 6) in Register 9 is set to 1.
If R9b5 is set to 1, light grey is obtained on output.
If R9b6 is set to 1, dark grey is obtained on output.
In the case where R9b5 and R9b6 are set to 0, the
normal operation is provided on output signals.
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