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參數(shù)資料
| 型號： | TDA9160 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | PAL/NTSC/SECAM decoder/sync processor(PAL/NTSC/SECAM譯碼器/ 同步處理器) |
| 中文描述： | COLOR SIGNAL DECODER, PDIP32 |
| 封裝： | 0.400 INCH, PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 7/27頁 |
| 文件大小： | 220K |
| 代理商： | TDA9160 |
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December 1991
7
Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM decoder/sync
processor
TDA9160
right-hand side (50 Hz) of the state
diagram.
Figure 6 illustrates the state diagram
of the 'norm' counter which is an
up/down counter that counts up if it
finds a vertical sync pulse within the
selected window. In the
NEAR-NORM and NORM states the
first correct vertical sync pulse after
one or more incorrect vertical sync
pulses is processed as an incorrect
pulse. This procedure prevents the
system from staying in the
NEAR-NORM or NORM state if the
vertical sync pulse is correct in the
first field and incorrect in the second
field. If no vertical sync pulse is found
in the selected window this will always
result in a down pulse for the 'norm'
counter.
Figure 7 illustrates the timing of the
display sandcastle (DSC) and the
reset pulse of the vertical sawtooth
with respect to the input signal
I
2
C-bus protocol
If the TXT output is connected to the
positive supply the address will
change from 8A to 8E.
Valid subaddresses = 00 to 0F
Auto-increment mode available for
subaddresses.
Subaddress 00 must always be sent
before subaddress 01 in order to
protect the horizontal output
transistor.
Table 1
Slave address (8A)
Table 2
Inputs
Table 3
Outputs
A6
1
A5
0
A4
0
A3
0
A2
1
A1
X
A0
1
R/W
X
SUBADDRESS
MSB
LSB
00
01
02
03
04
05
06
07
08
09
0A
0B
INA
FORF
SBL
INB
FORS
INC
DL
HU5
HS5
EW5
PW5
CP5
TC5
VS5
VA5
SC5
VSH5
IND
STB
HU4
HS4
EW4
PW4
CP4
TC4
CS4
VA4
SC4
VSH4
FOA
POC
HU3
HS3
EW3
PW3
CP3
TC3
VS3
VA3
SC3
VSH3
FOB
FM
HU2
HS2
EW2
PW2
CP2
TC2
VS2
VA2
SC2
VSH2
XA
SAF
HU1
HS1
EW1
PW1
CP1
TC1
VS1
VA1
SC1
VSH1
XB
FRQF
HU0
HS0
EW0
PW0
CP0
TC0
VS0
VA0
SC0
VSH0
ADDRESS
POR
FSI
STS
SL
PROT
SAK
SBK
FRQ
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