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參數(shù)資料
| 型號： | TDA9109/SN |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 偏轉(zhuǎn) |
| 英文描述： | HORIZ/VERT DEFLECTION IC, PDIP32 |
| 封裝： | SHRINK, PLASTIC, DIP-32 |
| 文件頁數(shù)： | 28/30頁 |
| 文件大?。?/td> | 266K |
| 代理商： | TDA9109/SN |
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HORIZONTAL SECTION
Operating Conditions
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VCO
R0(Min.)
Minimum Oscillator Resistor
Pin 6
6
k
C0(Min.)
Minimum Oscillator Capacitor
Pin 5
390
pF
F(Max.)
Maximum Oscillator Frequency
150
kHz
OUTPUT SECTION
I12m
Maximum Input Peak Current
Pin 12
5
mA
HOI
Horizontal Drive Output Maximum Current
Pin 26, Sunk current
30
mA
Electrical Characteristics (VCC = 12V, Tamb =25
oC)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
SUPPLY AND REFERENCE VOLTAGES
VCC
Supply Voltage
Pin 29
10.8
12
13.2
V
VDD
Supply Voltage
Pin 32
4.5
5
5.5
V
ICC
Supply Current
Pin 29
50
mA
IDD
Supply Current
Pin 32
5
mA
VREF-H
Horizontal Reference Voltage
Pin 13, I = -2mA
7.4
8
8.6
V
VREF-V
Vertical Reference Voltage
Pin 21, I = -2mA
7.4
8
8.6
V
IREF-H
Max. Sourced Current on VREF-H
Pin 13
5
mA
IREF-V
Max. Sourced Current on VREF-V
Pin 21
5
mA
1st PLL SECTION
HpolT
Delay Time for detecting polarity change
(see Note 3)
Pin 1
0.75
ms
VVCO
VCO Control Voltage (Pin 7)
VREF-H =8V
f0
fH(Max.)
1.3
6.2
V
Vcog
VCO Gain (Pin 7)
R0 = 6.49k
,C0 = 820pF,
dF/dV = 1/11R0C0
17.1
kHz/V
Hph
Horizontal Phase Adjustment (see Note 4)
% of Horizontal Period
±10
%
Vbmin
Vbtyp
Vbmax
Horizontal Phase Setting Value (Pin 8) (see Note 4)
Minimum Value
Typical Value
Maximum Value
Sub-Address 01
Byte x1111111
Byte x1000000
Byte x0000000
2.8
3.4
4.0
V
IPll1U
IPll1L
PLL1 Filter Current Charge
PLL1 is Unlocked
PLL1 is Locked
±140
±1
A
mA
f0
Free Running Frequency
R0 = 6.49k
,C0 = 820pF,
f0 = 0.97/8R0C0
22.8
kHz
df0/dT
Free Running Frequency Thermal Drift
(No drift on external components) (see Note 5)
-150
ppm/C
CR
PLL1 Capture Range
R0 = 6.49k
,C0 = 820pF,
from f0+0.5kHz to 4.5f0
fH(Min.)
fH(Max.)
90
25
kHz
FF
Forced Frequency
FF1 Byte 11xxxxxx
FF2 Byte 10xxxxxx
Sub-Address 02
2f0
3f0
Notes : 3. This delay is mandatory to avoid a wrong detection of polarity change in the case of a composite syn c.
4. See Figure 10 for explanation of reference phase.
5. These parameters are not tested on each unit. They are measured during our internal qualification.
6. This PLL capture range may be obtained only if f0 is captured (for instance bu adjusting R0). If not, more margin must be provided
between fH (Min.) and f0, to cope with the components spread.
910
9S
N
0
5
.T
B
L
TDA9109/SN
7/30
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