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參數(shù)資料
| 型號： | TDA9109/SN |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 偏轉 |
| 英文描述： | HORIZ/VERT DEFLECTION IC, PDIP32 |
| 封裝： | SHRINK, PLASTIC, DIP-32 |
| 文件頁數(shù)： | 14/30頁 |
| 文件大小： | 266K |
| 代理商： | TDA9109/SN |
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OPERATING DESCRIPTION (continued)
III - VERTICAL PART
III.1 - Function
23 VOUT
18 BREATH
VERT_AMP
SUB05/7bits
VMOIRE
SUB0C/5bits
VPOSITION
SUB06/7bits
22
20
SYNCHRO
OSCILLATOR
2
OSC
CAP
DISCH.
VSYNCIN
POLARITY
SAMPLING
CAPACITANCE
Vlow
Saw th.
Disch.
REF
TRANSCONDUCTANCE
AMPLIFIER
CHARGE CURRENT
VS_AMP
SUB07/6bits
COR_C
SUB08/6bits
S CORRECTION
C CORRECTION
91
09
S
N
3
5
.E
P
S
Figure 15 : AGC Loop Block Diagram
When the synchronization pulse is not present, an
internal current source sets the free running fre-
quency. For an external capacitor, COSC = 150nF,
the typical free running frequency is 100Hz.
The typical free running frequency can be calcu-
lated by :
f0
(Hz)= 1.5 105
1
COSC
A negative or positive TTL level pulse applied on
Pin 2 (VSYNC)as well as a TTLcomposite sync on
Pin 1 can synchronize the ramp in the range
[fmin , fmax]. This frequencyrange depends on the
ext e rn al capa c it or con nect ed on Pin 2 2.
A 150nF (
±5%) capacitor is recommended for
50Hz to 185Hz applications.
The typical maximum and minimum frequency, at
25
oC and without any correction (S correction or
C correction), can be calculated by :
f(Max.) = 3.5 x f0 and f(Min.) = 0.33 x f0
If S or C corrections are applied, these values are
slighty affected.
If a synchronization pulse is applied, the internal
oscillator is synchonized immediately but its
amplitude chan ges. An internal correction then
adjusts it in less than half a second. The top
value of the ramp (Pin 22) is sampled on the
AGC capacitor (Pin 20) at each clock pulse and
a transconduct ance amplifier modifies the
charge current of the capacitor in such a way to
make the amplitude again constant.
The read status register provides the vertical Lock-
Unlock and the vertical sync polarity information.
We recommend the use of an AGC capacitor with
low leakage current. A value lower than 100nA is
mandatory.
A good stability of the internal closed loop is
reached by a 470nF
± 5% capacitor value on
Pin 20 (VAGC).
TDA9109/SN
21/30
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