參數(shù)資料
型號(hào): TDA8779H
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 模擬信號(hào)調(diào)理
英文描述: 10-bit converter interface ADC/DAC for quadrature transceiver
中文描述: SPECIALTY ANALOG CIRCUIT, PQFP44
封裝: PLASTIC, QFP-44
文件頁(yè)數(shù): 8/20頁(yè)
文件大?。?/td> 112K
代理商: TDA8779H
1999 Sep 16
8
Philips Semiconductors
Product specification
10-bit converter interface (ADC/DAC) for
quadrature transceiver
TDA8779H
t
CL
t
r
t
f
A
NALOG SIGNAL PROCESSING
clock pulse width LOW
clock rise time
clock fall time
20
4
4
ns
ns
ns
Linearity
INLA
integral non linearity
ramp input;
f
CLK
= 20 MHz
full-scale; ramp input;
f
CLK
= 20 MHz
±
2.25
±
4
LSB
DNLA
differential non linearity
maximum missing codes
guaranteed: 20
+1.55 to
0.9 +2.8 to
1.1
LSB
Noise floor; note 1
NF
noise floor
f
i
= 4.43 MHz; 20 Msps
55
71
dB
Harmonics; note 2
THD
total harmonic distortion
f
i
= 4.43 MHz; 20 Msps
50
58
dB
Spurious free dynamic range
SFDR
spurious free dynamic
range
f
i
= 4.43 MHz; 20 Msps
50
58
dB
Matching between the I and Q channels
V
amplitude matching
f
i
= 4.43 MHz;
f
CLK
= 20 MHz;
T
amb
= 25
°
C
f
i
= 4.43 MHz;
f
CLK
= 20 MHz;
T
amb
= 25
°
C
0.1
6
%
phase matching
0.05
2
deg
Bandwidth
B
bandwidth (maximum
attenuation of
0.3 dB)
full-scale sine wave;
T
amb
= 25
°
C
50% full-scale sine wave;
T
amb
= 25
°
C
30
MHz
30
MHz
T
IMING
(
THE OUTPUT DATA IS AVAILABLE AFTER THE MAXIMUM DELAY TIME
t
d
); C
L
= 15 pF; T
amb
= 25
°
C (see Fig.3)
t
ds
sampling delay time
t
h
output hold time
t
d
output delay time
V
CCO
= 3.3 V
V
CCO
= 2.7 V
3-
STATE OUTPUT DELAY TIMES
; T
amb
= 25
°
C (see Fig.4)
t
dZH
output delay enable HIGH
t
dZL
output delay enable LOW
t
dHZ
output delay disable HIGH
t
dLZ
output delay disable LOW
5
12
13
11
ns
ns
ns
ns
10
7.7
15.5
14.9
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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