參數(shù)資料
型號: TDA8763
廠商: NXP Semiconductors N.V.
英文描述: 10-bit high-speed low-power ADC with internal reference regulator
中文描述: 10位高速低的內部參考調節(jié)功率ADC
文件頁數(shù): 8/24頁
文件大小: 174K
代理商: TDA8763
1999 Jan 06
8
Philips Semiconductors
Product specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8763
Reference voltages for the resistor ladder using the internal voltage regulator;
see Table 1
V
RB
V
RT
V
diff
reference voltage BOTTOM
reference voltage TOP
differential reference voltage
V
RT
V
RB
reference current
resistor ladder
temperature coefficient of the
resistor ladder
1.1
3.4
2.25
1.3
3.6
2.3
1.5
3.8
2.35
V
V
V
I
ref
R
lad
TC
Rlad
1.90
9.39
245
1860
456
175
175
1.95
2.00
mA
ppm
m
/K
mV
mV
V
V
offset(B)
V
offset(T)
V
i(p-p)
offset voltage BOTTOM
offset voltage TOP
analog input voltage
(peak-to-peak value)
note 2
note 2
note 3
Outputs
D
IGITAL OUTPUTS
D9
TO
D0
AND
IR (
REFERENCED TO
OGND)
V
OL
V
OH
I
OZ
LOW-level output voltage
HIGH-level output voltage
output current in 3-state mode
I
OL
= 1 mA
I
OH
=
1 mA
0.5 V < V
o
< V
CCO
0
V
CCO
0.5
20
0.5
V
CCO
+20
V
V
μ
A
Switching characteristics
C
LOCK INPUT
CLK; see Fig.4; note 1
f
clk(max)
maximum clock frequency
TDA8763M/3
TDA8763M/4
TDA8763M/5
clock pulse width HIGH
clock pulse width LOW
30
40
50
8.5
5.5
MHz
MHz
MHz
ns
ns
t
CPH
t
CPL
full effective bandwidth
full effective bandwidth
Analog signal processing
L
INEARITY
INL
DNL
E
offset
E
G
integral non-linearity
differential non-linearity
offset error
gain error (from device to device)
using internal reference voltage
f
clk
= 40 MHz; ramp input
f
clk
= 40 MHz; ramp input
middle code
note 4
±
0.8
±
0.5
±
1
±
3
±
2.0
±
0.9
LSB
LSB
LSB
%
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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