參數(shù)資料
型號(hào)： TDA8761M
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 9-bit analog-to-digital converter for digital video
中文描述： 1-CH 9-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PDSO28
封裝： 5.30 MM, PLASTIC, MO-150AH, SOT-341-1, SSOP-28
文件頁(yè)數(shù)： 9/20頁(yè)
文件大?。?/td> 93K
代理商： TDA8761M
1995 Mar 20
9
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
Notes
1.
In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.
Analog input voltages producing code 0 up to and including code 511:
a) V
osB
(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (V
RB
) at T
amb
= 25
°
C.
b) V
osT
(voltage offset TOP) is the difference between V
RT
(reference voltage TOP) and the analog input which
produces data outputs equal to code 511 at T
amb
= 25
°
C.
2.
3.
Analog input voltage range can be derived from V
RT
V
RB
difference. It is
4.
5.
6.
f
i
= 11 MHz and f
clk
= 30 MHz; f
i
= 8 MHz and f
clk
= 20 MHz.
The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No
glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.
The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB
×
6.02 + 1.76 dB.
Intermodulation measured relative to either tone with analog input frequencies of 10.0 MHz and 10.10 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.
10. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
digital-to-analog converter.
11. Output data acquisition: the output data is available after the maximum delay time of t
d
.
7.
8.
9.
3-state output delay times;
see Fig.4
t
dZH
t
dZL
t
dHZ
t
dLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
-------------------9
V
–
(
)
8
×
GER
V
-------------------------------------1.5 V
V
1.5 V
100
×
=
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