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參數(shù)資料
| 型號(hào)： | TDA8761M |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 9-bit analog-to-digital converter for digital video |
| 中文描述： | 1-CH 9-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | 5.30 MM, PLASTIC, MO-150AH, SOT-341-1, SSOP-28 |
| 文件頁(yè)數(shù)： | 7/20頁(yè) |
| 文件大小： | 93K |
| 代理商： | TDA8761M |
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1995 Mar 20
7
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
Reference voltages for the resistor ladder;
see Table 1
V
RB
V
RT
V
diff
reference voltage BOTTOM
reference voltage TOP
differential reference voltage
V
RT
V
RB
reference current
resistor ladder
temperature coefficient of the resistor
ladder
1.2
1.8
1.3
3.3
2.0
V
CCA
0.8 V V
3.0
V
V
I
ref
R
LAD
TC
RLAD
1.3
30
85
1.86
158
250
250
1.5
2.5
mA
ppm
m
/K
mV
mV
V
V
osB
V
osT
V
i(p-p)
offset voltage BOTTOM
offset voltage TOP
analog input voltage
(peak-to-peak value)
note 2
note 2
note 3
Outputs
D
IGITAL OUTPUTS
D8
TO
D0
AND
IR (
REFERENCED TO
OGND)
V
OL
V
OH
LOW level output voltage
HIGH level output voltage
I
O
= 1 mA
I
O
= 0 mA
I
O
=
0.4 mA
I
O
=
1 mA
0.4 V < V
O
< V
CCO
0
2.7
2.7
2.4
20
0.4
V
CCO
0.5
V
CCO
1.3
V
CCO
1.4
+20
V
V
V
V
μ
A
I
OZ
output current in 3-state mode
Switching characteristics
C
LOCK INPUT
CLK; see Fig.3; note 1
f
clk(max)
t
CPH
t
CPL
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
30
10
10
MHz
ns
ns
Analog signal processing
L
INEARITY
AINL
AC integral non-linearity
note 5; full scale input
sine wave
note 5; 50% full scale
input sine wave
note 5; full scale input
sine wave
note 5; 50% full scale
input sine wave
middle code;
V
RB
= 1.3 V; V
RT
= 3.3 V
V
RB
= 1.3 V;
V
RT
= 3.3 V; note 4
±
0.75
tbf
LSB
±
0.5
tbf
LSB
ADNL
AC differential non-linearity
±
0.5
tbf
LSB
±
0.3
tbf
LSB
OFER
offset error
±
1
LSB
GER
gain error (from device to device)
±
0.1
%
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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