參數(shù)資料
型號: TDA8758G
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: YC 8-bit low-power analog-to-digital video interface
中文描述: 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48
封裝: PLASTIC, SOT-313-2, LQFP-48
文件頁數(shù): 10/24頁
文件大小: 196K
代理商: TDA8758G
1996 Feb 01
10
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video
interface
TDA8758
Notes
1.
2.
0 dB is obtained at the AGC amplifier when applying V
I(p-p)
= 1.0 V on Y channel.
It is recommended that the rise and fall times of the clock are
1 ns. In addition, a ‘good layout’ for the digital and
analog grounds is recommended.
3.
THD (total harmonic distortion) is obtained with the addition of the first five harmonics:
(2nd)2
+
+
+
a) F being the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.
Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB
×
6.02 + 1.76 dB.
Measurement carried out using video analyser VM700A, where video analog signal is reconstructed through a
digital-to-analog converter.
4.
5.
6.
The supply voltage ripple rejection is the relative variation of the analog signal (full-scale signal at input) for 0.5 V of
supply variation:
V
V
CCA
Timing (f
clk
= 32 MHz);
see Fig.9
D
IGITAL OUTPUTS
(C
L
= 15 pF)
t
ds
sampling delay time
t
h
output hold time
t
d
output delay time
t
W
clamp pulse width
10
2
2
15
3
18
ns
ns
ns
μ
s
see Figs 6 and 7
3-state output delay times;
see Fig.10
t
dZH
t
dZL
t
dHZ
t
dLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
12
10
58
70
14
12
62
74
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
THD
20 log
(3rd)2
(4th)2
(5th)2
(6th)2
+
----------------------------------------------------F
=
SVRR2
I FF
)
V
I 00
V
I FF
(
)
×
----------------------------V
=
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