參數(shù)資料
型號(hào): TDA8753A
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 模擬信號(hào)調(diào)理
英文描述: YUV 8-bit analog-to-digital interface
中文描述: SPECIALTY ANALOG CIRCUIT, PDIP42
封裝: 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42
文件頁(yè)數(shù): 6/20頁(yè)
文件大?。?/td> 111K
代理商: TDA8753A
1996 Jan 12
6
Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
TDA8753A
The TDA8753A registers have address F0, F1 and F2
hexadecimal notation. Whenever the received address
(decoded on the first 8 bits received) is one of these, the
event is recorded in such a way that the next data received
by the TDA8753A will be captured in the line
buffer BF0, BF1 and BF2 respectively.
When 8 bits have been received, the data reception state
is entered. The address reception state can also be exited
at any time when V50 goes HIGH. The F0, F1 and F2
registers may not be loaded properly if there is some
activity in progress on the incoming line.
D
ATA RECEPTION STATE
The next 8 bits are considered as data bits according to
the format of Fig.4.
When 8 data bits have been received, the data is recorded
in the BF0, BF1 or BF2 line buffers if the previous address
recorded was F0 hex, F1 hex or F2 hex respectively.
The bit count is then reset to zero and the address
reception state is entered. This state may be ended any
time when V50 goes HIGH but in that condition F0, F1 and
F2 registers may not be loaded properly.
Table 1
Data allocation
ADDRESS
PARAMETER
FUNCTION
NUMBER
OF BITS
BIT
POSITION
F0H
CF
compression factor value will be (1 + cf/255)
which results in a range from 1 to 2
coring definition in U and V channels; see Table 5
notch filter selection in U and V channels
(0 = 4 MHz; 1 = 2 MHz)
luminance prefilter active
notch prefilter active
DTO control
select DTO reset (0 = WE; 1 = H
ref
)
select delay in WEO
luminance delay compression (see Table 5)
not used; load 0
8
7:0
F1H
UV_CORING
UV_FILTER_TYPE
2
1
1:0
2
PRE_ON
NOTCH_ON
DTO_ON
SEL_DTO_RES
WEO_DEL_SEL
Y_VAR_DELAY
1
1
1
1
3
4
5
6
F2H
5
7:2
Fig.4 Data reception.
handbook, halfpage
1
1
0
X
X
X
X
X
MBE427
last address
bit received
first data bit of value
(e.g. for address F2 register)
first bit of next
address stream
Data value is F2 0:2 = 110(DEL 0:2 )
incoming stream
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