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參數(shù)資料
| 型號： | TDA8745 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Satellite sound receiver with IIC-bus control(IIC總線控制的衛(wèi)星聲音接收器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件頁數(shù)： | 18/40頁 |
| 文件大小： | 261K |
| 代理商： | TDA8745 |
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1996 Mar 11
18
Philips Semiconductors
Preliminary specification
Satellite sound receiver with I
2
C-bus control
TDA8745
Table 19
Bits DEM1 and DEM0; De-emphasis; note 1;
see Fig.5
Notes
1.
Different de-emphasis characteristics can be selected,
to adjust for different main channel audio carriers.
In most cases the de-emphasis needed for main
channel carriers is 50
μ
s.
The NR is to be used with the 75
μ
s setting for
standard secondary channels.
2.
3.
Table 20
Bit BPFN; Band-Pass Filter Not; note 1
Note
1.
To avoid interference by the video signal, the incoming
baseband signal is filtered. If this filtering is not
required the filter can be switched off.
DEM1
a2
DEM0
a1
DE-EMPHASIS
0
0
1
1
0
1
0
1
no de-emphasis (flat)
J17
50
μ
s
(2)
75
μ
s [por]
(3)
BPFN
a0
DESCRIPTION
0
mixer input signal filtered by BPF
(after POR)
mixer input signal is not filtered
1
Slave transmitter mode (bits transmitted from
TDA8745 to microcontroller)
Table 21
Bit PDL; Presence Detector Left; note 1
Note
1.
Bit PDL (r7) transmits the current status of the left
channel presence detector. When PDL = 1, no carrier
is found at the currently selected frequency. If bit
PDM (s3) = 0 the left channel audio is muted.
Table 22
Bit PDR; Presence Detector Right; note 1
Note
1.
Bit PDR (r6) transmits the current status of the right
channel presence detector. When PDR = 1, no carrier
is found at the currently selected frequency. If bit
PDM (s3) = 0 the right channel audio is muted.
PDL
r7
DESCRIPTION
0
1
carrier detected at left channel
no carrier detected at left channel
PDR
r6
DESCRIPTION
0
1
carrier detected at right channel
no carrier detected at right channel
Table 23
Bit POR; Power-On Reset; note 1
Note
1.
At switching on, or after a power dip on the I
2
C-bus supply voltage (V
P2
), an internal signal is generated which resets
the I
2
C-bus registers to a pre-defined state. If bit POR (r0) = 1, such a situation has occurred since the last time the
read byte was read. After reading, the bit is reset to logic 0.
Table 24
Bits r5 to r1
POR
r0
DESCRIPTION
0
1
normal operation
POR generated; power dip detected since last read of POR bit
r5
r4
r3
r2
r1
DESCRIPTION
1
1
1
1
1
These bits have no function. Although their state is fixed, the microcontroller
should not rely on this because of eventual future use.
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