參數(shù)資料
型號(hào)： TDA8722M-T
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PDSO20
文件頁(yè)數(shù)： 27/28頁(yè)
文件大?。?/td> 155K
代理商： TDA8722M-T
1998 Jun 23
8
Philips Semiconductors
Product specication
I2C-bus programmable modulator for
negative video modulation and FM sound
TDA8722
The bits T0 to T2 are available for test purposes and the possibilities are shown in Table 5.
Table 5
Test modes
Notes
1. In ‘TPSG on’ mode the video carrier is modulated by the test signal consisting of a synchronization pulse and two
vertical white bars on a black screen. This mode should be selected to adjust the TV set receiving the modulated
signal to the right frequency.
2. In ‘RF oscillator off’ mode, the RF oscillator and the RF mixer are switched-off and there is no RF carrier coming out
of the device. This mode can be selected to avoid RF radiation to other parts when the modulator output is not used.
3. In ‘balance test’, the video carrier is over modulated. This simplifies residual carrier measurements.
4. In ‘fref’ and ‘fDIV’ modes, the reference frequency fref in the phase comparator or the divided RF oscillator frequency
fDIV is available on the output Port pin. This mode requires that bit P0 = 0.
5. The ‘high-impedance test’ mode may be used to inject an external tuning voltage to the RF tank circuit, to test the
oscillator. In this mode, the phase detector is disabled and the external transistor of the tuning amplifier is
switched-off. The AMP output (pin 7) is LOW (<200 mV).
6. In the ‘phase detector disabled’ mode, it is possible to measure the leakage current at the input of the tuning amplifier,
on the CP pin. In this mode the RF oscillator is off, and the baseband TV channel signal is present on the RF outputs
for testing the audio and video parts.
T0
T1
T2
OPERATIONAL MODE
0
normal operation
0
1
Test Pattern Signal Generator (TPSG) on; note 1
0
1
0
RF oscillator off; note 2
0
1
balance test; note 3
100
fref out (if p0 = 0); note 4
1
0
1
high-impedance test; note 5
110
fDIV out (if p0 = 0); note 4
1
phase detector disabled; baseband signals on RF outputs; note 6
The possibilities of bit P0, which controls the output Port
(pin 14) are given in Table 6.
The Port is an NPN open-collector type. For monitoring the
fref or fDIV frequency on the output Port, the P0 bit must be
logic 0 to let the output Port free.
Table 6
Output Port programming
P0
OUTPUT PORT STATE
0
off; high impedance
1
on; sinking current
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