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參數(shù)資料
| 型號： | TDA8705T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 6-bit high-speed dual Analog-to-Digital Converter ADC |
| 中文描述： | DUAL 2-CH 6-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 117K |
| 代理商： | TDA8705T |
1996 Jan 12
8
Philips Semiconductors
Product specification
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
TDA8705
Notes
1.
In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
Analog input voltages producing code 00 up to and including 3F:
a) V
osB
(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (V
RB
) at T
amb
= 25
°
C.
b) V
osT
(voltage offset TOP) is the difference between V
RT
(reference voltage TOP) and the analog input which
produces data outputs equal to 3F at T
amb
= 25
°
C.
Full-scale sine wave (f
i
= 10 MHz; f
clk
= 40 MHz).
The Offset Error (OFE) and Gain Error (GE) are determined by taking results from a simultaneous acquisition on both
ADCs of a sine wave greater than full-scale. The occurrences of code 0 and 63 are used to calculate the OFE
(mid-scale-to-mid-scale) and the GE (amplitude difference) between the two converters A and B.
The
0.5 dB analog bandwidth is determined by the 0.5 dB reduction in the reconstructed output, the input being a
full-scale sine wave. It is determined with a beat frequency method; no glitches occurrence.
The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB
×
6.02 + 1.76 dB.
Intermodulation measured relative to either tone with analog input frequencies of 10.0 MHz and 10.1 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.
Output data acquisition: the output data is available after the maximum delay time of t
d
.
2.
3.
4.
5.
6.
7.
8.
9.
B
IT ERROR RATE
BER
bit error rate
f
clk
= 40 MHz;
f
i
= 10 MHz;
V
I
=
±
16 LSB at code 32
10
13
times/
samples
Timing; f
clk
= 40 MHz; C
L
= 15 pF;
note 9; see Fig.3
t
ds
t
h
t
d
sampling delay time
output hold time
output delay time
5
2
14
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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相關代理商/技術參數(shù) |
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|---|---|
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