參數(shù)資料
型號: TDA8705T
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: 6-bit high-speed dual Analog-to-Digital Converter ADC
中文描述: DUAL 2-CH 6-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
文件頁數(shù): 7/16頁
文件大小: 117K
代理商: TDA8705T
1996 Jan 12
7
Philips Semiconductors
Product specification
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
TDA8705
Switching characteristics
C
LOCK INPUT
CLK; note 1; see Fig.3
f
clk(max)
t
CPH
t
CPL
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
40
10
10
MHz
ns
ns
Analog signal processing
L
INEARITY
ILE
DLE
AILE
OFE
DC integral linearity error
DC differential linearity error
AC integral linearity error
offset error between A and B
±
1
±
0.25
±
0.25
±
0.5
±
0.5
±
0.5
±
1.0
±
2
LSB
LSB
LSB
LSB
note 3
f
i
= 10 MHz;
f
clk
= 40 MHz; note 4
f
i
= 10 MHz;
f
clk
= 40 MHz; note 4
input voltage floating
GE
gain error between A and B
±
1
±
2
LSB
MID
middle scale output code A and B
31
32
B
ANDWIDTH
; f
clk
= 40 MHz
B
0.5 dB analog bandwidth
full-scale sine wave;
note 5
full-scale square wave;
Fig.4; note 6
full-scale square wave;
Fig.4; note 6
50
MHz
t
STLH
analog input settling time LOW-to-HIGH
8
ns
t
STHL
analog input settling time HIGH-to-LOW
5
ns
H
ARMONICS
; f
clk
= 40 MH
Z
; see Fig.5
h
1
fundamental harmonics (full scale)
h
all
harmonics (full scale);
all components
second harmonics
third harmonics
THD
total harmonic distortion
f
i
= 10 MHz
f
i
= 10 MHz
0
dB
49
51
46
40
dB
dB
dB
f
i
= 10 MHz
S
IGNAL
-
TO
-
NOISE RATIO
; note 7; see Fig.5
S/N
signal-to-noise ratio (full scale)
without harmonics;
f
clk
= 40 MHz;
f
i
= 10 MHz
34
37
dB
E
FFECTIVE BITS
; note 7; see Figs 5 and 6
EB
effective bits
f
clk
= 40 MHz
f
i
= 10 MHz
f
i
= 20 MHz
5.8
5.6
bits
bits
T
WO
-
TONE
; note 8
TTIR
two-tone intermodulation rejection
f
clk
= 40 MHz
48
dB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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