- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄383989 > TDA8703 (NXP SEMICONDUCTORS) 8-bit high-speed analog-to-digital converter PDF資料下載
參數(shù)資料
| 型號(hào)： | TDA8703 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 8-bit high-speed analog-to-digital converter |
| 中文描述： | 1-CH 8-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PDIP24 |
| 封裝： | 0.600 INCH, PLASTIC, MO-015AD, SOT-101-1, DIP-24 |
| 文件頁(yè)數(shù)： | 3/18頁(yè) |
| 文件大小： | 141K |
| 代理商： | TDA8703 |
第1頁(yè)第2頁(yè)當(dāng)前第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)
1996 Aug 26
3
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
QUICK REFERENCE DATA
Notes
1.
2.
3.
Full-scale sinewave (f
i
= 4.4 MHz; f
CLK
; f
CLK
= 27 MHz).
The
3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at input).
The circuit has two clock inputs CLK and CLK. There are four modes of operation:
a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the LOW-to-HIGH transition of the input clock signal.
b) TTL (mode 2); CLK decoupled to DGND by a capacitor.CLK input is TTL threshold voltage of 1.5 V and sampling
on the HIGH-to-LOW transition of the input clock signal.
c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V
(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the
clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.
d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF
capacitor.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CCA
V
CCD
V
CCO
I
CCA
I
CCD
I
CCO
ILE
DLE
AILE
B
f
CLK
/f
CLK
P
tot
analog supply voltage
digital supply voltage
output stages supply voltage
analog supply current
digital supply current
output stages supply current
DC integral linearity error
DC differential linearity error
AC integral linearity error
3 dB bandwidth
maximum conversion rate
total power dissipation
4.5
4.5
4.2
40
5.0
5.0
5.0
28
19
11
19.5
290
5.5
5.5
5.5
36
25
14
±
1
±
1/2
±
2
415
V
V
V
mA
mA
mA
LSB
LSB
LSB
MHz
MHz
mW
note 1
note 2; f
CLK
= 40 MHz
note 3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TDA8703T | 8-bit high-speed analog-to-digital converter |
| TDA8705A | 6-bit high-speed dual Analog-to-Digital Converter ADC |
| TDA8705AT | 6-bit high-speed dual Analog-to-Digital Converter ADC |
| TDA8705 | 6-bit high-speed dual Analog-to-Digital Converter ADC |
| TDA8705T | 6-bit high-speed dual Analog-to-Digital Converter ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA8703T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit high-speed analog-to-digital converter |
| TDA8705 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:6-bit high-speed dual Analog-to-Digital Converter ADC |
| TDA8705A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:6-bit high-speed dual Analog-to-Digital Converter ADC |
| TDA8705AT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:6-bit high-speed dual Analog-to-Digital Converter ADC |
| TDA8705ATD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 6-Bit |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。