參數(shù)資料
型號(hào): TDA8703
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: 8-bit high-speed analog-to-digital converter
中文描述: 1-CH 8-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PDIP24
封裝: 0.600 INCH, PLASTIC, MO-015AD, SOT-101-1, DIP-24
文件頁數(shù): 14/18頁
文件大小: 141K
代理商: TDA8703
1996 Aug 26
14
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
APPLICATION INFORMATION
Additional application information will be supplied upon request (please quote number FTV/8901).
Fig.13 Application diagram.
handbook, full pagewidth
MGA014 - 1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
TDA8703
TDA8703T
D0
D1
D2
D3
D4
D5
D6
DGND
CLK
AGND
DEC
VI
O / UF
D7
n.c.
CLK
CE
VRB
VRT
VCCA
VCCD
n.c.
VCCO
TC
DGND
AGND
100 pF
47 pF
4.7
μ
F
22 nF
22 nF
22 nF
5 V
22
(1)
4.7
μ
F
CLK should be decoupled to the DGND with a 100 nF capacitor, if a TTL signal is used on CLK (see Chapter “Characteristics”, note 1).
CLK and CLK can be used in a differential mode (see Chapter “Characteristics”, note 1).
V
RB
and V
RT
are decoupling pins for the internal reference ladder; do not draw current from these pins in order to achieve good linearity.
If it is required to use the TDA8703 in a parallel system configuration, the references (V
and V
RT
) of each TDA8703 can be connected together.
Code 0 will be identical and code 255 will remain in the 1 LSB variation for each TDA8703.
Analog and digital supplies should be separated and decoupled.
Pins 6 and 10 should be connected to AGND in order to prevent noise influence.
(1) It is recommended to decouple V
CCO
through a 22
resistor especially when the output data of the TDA8703 interfaces with a capacitive CMOS
load device.
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