參數(shù)資料
型號: TDA8376A
廠商: NXP Semiconductors N.V.
英文描述: I2C-bus controlled PAL/NTSC TV processors
中文描述: I2C總線控制的PAL / NTSC制式電視處理器
文件頁數(shù): 15/44頁
文件大小: 249K
代理商: TDA8376A
1996 Jan 26
15
Philips Semiconductors
Objective specification
I
2
C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
Table 12
Vertical divider mode
Table 13
Video identification mode
Table 14
Long blanking mode
Table 15
EHT tracking mode
Table 16
Enable vertical guard (RGB blanking)
Table 17
Service blanking
Table 18
Overvoltage input mode
Table 19
Vertical deflection mode (TDA8376 only)
NCIN
VERTICAL DIVIDER MODE
0
1
normal operation
switched to search window
VID
VIDEO IDENTIFICATION MODE
1
loop switched on and off
not active
0
1
LBM
BLANKING MODE
0
1
adapted to standard (50 or 60 Hz)
fixed in accordance with 50 Hz standard
HCO
TRACKING MODE
0
1
EHT tracking only on vertical
EHT tracking on vertical and E-W
EVG
VERTICAL GUARD MODE
0
1
not active
active
SBL
SERVICE BLANKING MODE
0
1
off
on
PRD
OVERVOLTAGE MODE
0
1
detection mode
protection mode
EXP
CL
VERTICAL DEFLECTION MODE
0
0
1
1
0
1
0
1
normal
compress
expand
expand and lift
Table 20
Condition Y/C input
Table 21
PAL/NTSC matrix
Table 22
Y-delay adjustment; note 1
Note
1.
For an equal delay of the luminance and chrominance
signal the delay must be set at a value of 160 ns. This
is only valid for a CVBS signal without group
delay distortions.
Table 23
RGB blanking
Table 24
Noise coring (peaking)
Table 25
Enable fast blanking RGB1
Table 26
Enable fast blanking RGB2
CVS
Y-INPUT MODE
0
1
switched to Y/C mode
switched to CVBS mode
MAT
MATRIX
0
1
adapted to standard
PAL
YD0 to YD3
Y-DELAY
YD3
YD2
YD1
YD0
YD3
×
160 ns +
YD2
×
80 ns +
YD1
×
40 ns +
YD0
×
40 ns
RBL
RGB BLANKING
0
1
not active
active
COR
NOISE CORING
0
1
off
on
IE1
FAST BLANKING
0
1
not active
active
IE2
FAST BLANKING
0
1
not active
active
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