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參數(shù)資料
| 型號： | TDA8350 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | DC-coupled vertical deflection and East-West output circuit |
| 中文描述： | DC耦合垂直偏轉(zhuǎn)和東，西輸出電路 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 115K |
| 代理商： | TDA8350 |
January 1995
7
Philips Semiconductors
Preliminary specification
DC-coupled vertical deflection and
East-West output circuit
TDA8350Q
Notes
1.
A flyback supply voltage of
>
50 V up to 60 V is allowed in application. A 220 nF capacitor in series with a 22
resistor
(dependent on I
O
and the inductance of the coil) has to be connected between pin 7 and ground. The decoupling
capacitor of V
FB
has to be connected between pin 8 and pin 4. This supply voltage line must have a resistance of
33
(see application circuit Fig.5).
The linearity error is measured without S-correction and based on the same measurement principle as performed on
the screen. The measuring method is as follows:
Divide the output signal I
5
- I
9
(V
RM
) into 22 equal parts ranging from 1 to 22 inclusive. Measure the value of two
succeeding parts called one block starting with part 2 and 3 (block 1) and ending with part 20 and 21 (block 10). Thus
part 1 and 22 are unused. The equations for linearity error for adjacent blocks (LEAB) and not adjacent blocks (NAB)
are given below;
a
a
)
–
a
avg
a
avg
2.
;
3.
4.
Referenced to V
P
.
V values within formulae, relate to voltages at or between relative pin numbers, i.e. V
9-5
/V
1-2
= voltage value across
pins 9 and 5 divided by voltage value across pins 1 and 2.
V
3-5
AC short-circuited.
Frequency response V
9-5
/V
3-5
is equal to frequency response V
9-5
/V
1-2
.
At V
(ripple)
= 500 mV eff; measured across R
M
; f
i
= 50 Hz.
The output pin 11 requires a capacitor of minimum value 68 nF.
5.
6.
7.
8.
East-West amplifier
V
O(sink)
saturation voltage
I
O(sink)
= 500 mA;
I
I(corr)
= 0
μ
A; note 8
2.0
2.5
V
G
v
f
res
LE
open loop voltage gain (V
11
/V
12
)
frequency response (
3 dB)
linearity error
47
4000
1
1
1
0.5
2
0.3
dB
Hz
%
%
μ
A
V
mA
V
V
O(sink)
= 3 V
V
O(sink)
= 10 V; note 2
I
bias
V
I(DC)
I
set
V
13-7
input bias current (pin 12)
DC input voltage
offset voltage set current
maximum allowed voltage at
pin 13
Guard circuit
I
O
output current
not active;
V
O(guard)
= 0 V
active; V
O(guard)
= 4.5 V
I
O
= 100
μ
A
maximum leakage
current = 10
μ
A
50
μ
A
output current
output voltage
allowable voltage on pin 10
1
2.5
5.5
40
mA
V
V
V
O(guard)
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
LEAB
-----------------------------
=
NAB
max
a
a
min
–
=
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| TDA8350Q | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DC-coupled vertical deflection and East-West output circuit |
| TDA8350Q/N6,112 | 功能描述:IC DC COUPLED V-DEFL 13-SIL RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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| TDA8351A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DC-coupled vertical deflection output circuit |
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