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參數(shù)資料
| 型號： | TDA8050A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | QPSK transmitter |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO32 |
| 封裝： | PLASTIC, SO-32 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 125K |
| 代理商： | TDA8050A |
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1999 Nov 05
9
Philips Semiconductors
Product specification
QPSK transmitter
TDA8050A
Notes
1.
All specification points of the output section and the overall circuit are measured after the 2 : 1 transformer (Siemens
V944) loaded with 75
.
Overall phase noise:
a) Converter: I
(cp)
= 0.36 mA; f
ref
= 25 kHz.
b) I and Q = 100 mV
dif
.
c) DAC = 28.
d) f = 65 MHz.
The crystal oscillator uses a 4, 2 or 1 MHz crystal in series with a capacitor. The crystal is serial resonant with a load
capacitance of 18 to 20 pF. The connection to V
CC
is preferred but it might also be to GND.
2.
3.
Crystal oscillator
f
xtal
Z
i
V
i(DC)
Modulator synthesizer
crystal frequency
input impedance
DC input level
note 3
f
xtal
= 4 MHz
1
600
1200
2.9
4
MHz
V
f
ref(mod)
RDR1
reference frequency
programmablereferencedivider
ratio
fix main divider ratio
charge-pump current
4
250
16
kHz
ND1
I
(cp)
Converter synthesizer
1120
0.30
fixed
mA
f
step
RD2
RDR2
step size
fix reference divider ratio
programmablereferencedivider
ratio
fix main divider ratio
programmable main divider
ratio
100
4
2
500
160
kHz
see Tables 4 and 5
ND2
NDR2
290
4
1800
see Tables 4 and 5
3-wire bus
V
IL
V
IH
Lock detect pin
input LOW level
input HIGH level
2.4
0.8
V
V
V
O(lock)
V
O(unlock)
Serial control clock
output voltage (LOCK)
output voltage (UNLOCK)
5
0.02
V
V
f
clk
t
su
t
h(CLK)
t
d(strt)
t
d(stp)
clock frequency
input data to CLK set-up time
input data to CLK hold time
delay to rising clock edge
delay from last clock edge
330
2
1
3
3
kHz
μ
s
μ
s
μ
s
μ
s
see Fig.8
see Fig.8
see Fig.8
see Fig.8
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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