參數(shù)資料
型號(hào)： TDA7719
廠商： STMICROELECTRONICS
元件分類： 音頻控制
英文描述： 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDSO28
封裝： ROHS COMPLIANT, MO-153AC, TSSOP-28
文件頁(yè)數(shù)： 6/46頁(yè)
文件大小： 590K
代理商： TDA7719
Description
TDA7719
Doc ID 13698 Rev 4
With different input configuration, the input source can be selected with input selector
(Byte0/1 Bit0~Bit2). The following matrix defines the selector configuration of different input
sources dependant on the configuration bits.
Note:
In each configuration, only the light grey cells are allowed. The dark grey cells are not
allowed.
MD1/MD2 selection is defined by extra bit – ‘MD1/2 selection’ in I2C control table (Bit3 of
Byte0/1).
The input stage can be configured to 0dB or 3dB gain with I2C bus. The 0dB configuration
allows up to 2Vrms input signal level, while with 3dB gain, the internal signal will start to clip
when input signal level is higher than 1.414Vrms.
The Pin10~Pin13 can be configured as full differential input stage or quasi-differential input.
When it is configured as quasi-differential input, both Pin11 and Pin12 are used as the QD
common input pins. These two pins must be connected together externally in application. In
this case the input impedance of QD4 common is reduced to 50k
Ω (half of QD4 left and
right input). The diagram below shows both QD and FD configuration of QD4/FD4.
Table 7.
Selector configuration matrix
Selector Bits
(Byte0/1
Bit2~Bit0)
000
001
010
011
100
101
110
111
IN0IN1
IN2IN3
IN4IN5
IN6
IN7
CFG0
QD1
QD2
QD3
QD4
NA
CFG1
SE1
SE3
QD3
QD4
SE2
NA
CFG2
SE1
SE3
QD3
NA
SE2
SE4
SE5
NA
CFG3
SE1
SE3
QD3
MD1/2
SE2
NA
CFG4
QD1
QD2
QD3
FD
NA
CFG5
QD1
QD2
QD3
NA
SE4
SE5
NA
CFG6
NA
SE3
QD3
FD
SE2
NA
MD3
CFG7
SE1
SE3
QD3
FD
SE2
NA
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