參數(shù)資料
型號: TDA7531
廠商: STMICROELECTRONICS
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: TQFP-64
文件頁數(shù): 9/11頁
文件大?。?/td> 117K
代理商: TDA7531
RECOMMENDED OPERATING CONDITIONS (AGND, DGND, all voltages with respect to 0V)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
VDD
VCC
Power Supplies
Digital
Analog
3.15
3.3
3.45
V
Tamb
Operating Ambient
Temperature
25
°C
GENERAL CHARACTERISTICS (Tamb = 25°C; VDD, VCC 3.3V)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
DIGITAL CHARACTERISTICS
VIH
High Level Input Voltage
VDD-0.1
V
VIL
Low Level Input Voltage
0.1
V
VOH
High Level Output Voltage
VDD-0.1
V
VOL
Low Level Output Voltage
0.1
V
Input Leakage Current
(Digital Inputs)
TBD
A
Output Leakage Current
TBD
A
POWER CHARACTERISTICS
Digital Supply Power
(Note 10) Estimated
mW
Analog Supply Power
(Note 10)
mW
Total Power Consumption
(Note 10)
300
mW
Note 10: The measure is done with VDD, VCC = 3.3V; FS = 44.1kHz * 256 and with all the DAC, ADC and PLL working.
Serial Audio Interface
This interface is split into two fully independent
sections, one for data inputs (Receiver section)
and the other for data outputs (Transmitter sec-
tion), which can operate either in master (sync
signal are generated by the device) or in slave
(sync signals are input from an external source)
mode.
SCKR and SCKT are the bit clocks used for re-
spectively receiving and transmitting the audio
data; LRCKR and LRCKT are used to indicate
Left and Right data transmission and reception,
and the start of a new sample period. LRCKR fre-
quency is always equal to the audio sampling
rate fs. SDI0, SDI1 and SDI2 are the serial data
input pins for DAC #0, #1 and #2 respectively,
output data from ADC #0 and #1 are presented
on SDO0 and SDO1.
Many different formats can be used for data
transmission; a list of the available options which
can be chosen via software setup follows.
16, 24 and 32 bits per LRCK frame formats are
allowed
Data bytes can be sent from MSB to LSB or
vice-versa
When the 32-bits format
1 is chosen, data can
be left or right justified
Left/Right channel data can be associated to
either LRCK polarity
Data can be set to vary on either the leading
LRCK edge or the falling one
Data transmission can be delayed of one SCK
clock cycle
Control Interface
Control for the functions available on the device
is sent through this SPI-like interface. The
TDA7531 works always as a slave device; infor-
mation is exchanged through 8-bit bytes (MSB
first); an error condition is flagged if a non-integer
multiple of eight SCK pulses is transmitted. SCN
control port bit clock (input into the device from
the master device), MOSI is the input data line
and MISO the output one. The device accepts
two of the four original Motorola transfer formats:
CPHA=0/CPOL=0 and CPHA=1/CPOL=1.
To set a device function (write to a register), CSN
must be kept low. The first three bits on MOSI are
ignored; the next four bit form the memory Ad-
dress Pointer (MAP), which is set to the address
of the register (function) that has to be updated.
The last bit of the first byte is a read/write indica-
tor (R/W), which should be high to write. The next
8 bit are the data which will be placed into the
register
designated
by
MAP,
all
hardware
changes will happen at the end of the data byte,
while operations on non-existing or reserved ad-
dresses will have no effect.
1This format assumes transmission and reception of 24-bit-long data words with 32 SCK cycles per LRCK frame.
TDA7531
7/11
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