
To read from a register, bring CSN low and send
the desired MAP address on MOSI, with the R/W
bit low; the content of the addressed register will
be clocked out on the MISO line during the next 8
SCK pulses.
The TDA7531 has a MAP auto increment capa-
bility: when more than two bytes are transmitted
between assertion and dessertion of CSN, the
3rd byte is interpreted as the data byte for
MAP+1, the 4th one as the data byte for MAP+2
and so on (read or write is set once in the first
byte).
During transmission of the first byte, the status
Register value (see below) will be output on the
MISO line; the same is true for successive bytes
if a writing operation is being performed or if the
MAP value addressed for read operation is non-
existing, reserved or corresponding to an unread-
able register.
CONTROLL PORT BIT DEFINITION
Memory Address Pointer (MAP) Byte
B7
B6
B5
B4
B3
B2
B1
B0
X
MAP3
MAP2
MAP1
MAP0
R/W
— MAP3 to MAP0: Register Functions
0
1
2
3
4
5
6
7
8
9
10
11
12
Reserved
Output Attenuator 1 (DAC #0 LEFT)
Output Attenuator 2 (DAC #0 RIGHT)
Output Attenuator 3 (DAC #1 LEFT)
Output Attenuator 4 (DAC #1 RIGHT)
Output Attenuator 5 (DAC #2 LEFT)
Output Attenuator 6 (DAC #2 RIGHT)
All Output Attenuator
*)
Mute Controll
Clock and PLL
SAI Trasmitter Configuration
SAI Receiver Configuration
Status Report Byte
— R/W
Read/Write
0
1
Read Data
Write Data
*) Unreadable register
DATA BYTES DEFINITION
Output Attenuator Control Byte
B7
B6
B5
B4
B3
B2
B1
B0
MOD ATT4 ATT3 ATT2 ATT1 ATT0 ATF1 ATF0
— ATT4 to ATT0: Corse attenuation 1.5dB step
— ATF2 to ATF1 Fine attenuation 0.4dB step
— MODE: Normal/Step Volume Mode
0
1
Normal Volume Mode
Step Volume Mode
*)
*) Even when the step volume mode is enabled,
the target value of attenuation must be specified
by ATT - ATF bits.
Mute Control Byte
B7
B6
B5
B4
B3
B2
B1
B0
X
Busy
Mut6 Mut5 Mut4 Mut3 Mut2
Mut1
— MAP3 to MAP0: Register Functions
Mutn = 0 Channel n not muted
Mutn = 1 Channel n muted
— Busy
Mute in progress Flag (read only)
0
1
Mute operations complete
Mute operations in progress
Clock and PLL Control Byte
B7
B6
B5
B4
B3
B2
B1
B0
X
ADCclk MODE CO1 CO0
CI1
CI0
— CI1-CI0
Input Frequency Selection
0
1
2
3
Master Clock Frequency = 256fs
Master Clock Frequency = 384fs
Not Used
Master Clock Frequency = 512fs
—
CO1-CO0 Output Frequency Selection
0
1
2
3
CKOUT Frequency = 32KHzfs
CKOUT Frequency = 44.1KHzfs
Not Used
CKOUT Frequency = 48KHzfs
—
MODE
ADC Operating Mode
QUARTZ CLKSELL
pin
12.288
0
Oscillator Selected
27MHz
1
PLL Selected
SAI Trasmitter Control Byte
B7
B6
B5
B4
B3
B2
B1
B0
Twdt
Trel
Tckp
Tlrs
Tdir
Twl1
Twl0
Tmst
— Twdt
32-bit
Output
Data
Word
Justification
0
1
Left-Justified 24-bit Data Word
Right-Justfied 24-bit Data Word
— Trel
One-Cycle Data Delay
TDA7531
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