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參數(shù)資料
| 型號(hào)： | TDA6500TT/C4,118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 調(diào)諧器 |
| 英文描述： | 3-BAND, VIDEO TUNER, PDSO32 |
| 封裝： | 6.10 MM, 0.65 MM PITCH, PLASTIC, MO-153, SOT487-1, TSSOP-32 |
| 文件頁數(shù)： | 37/37頁 |
| 文件大?。?/td> | 223K |
| 代理商： | TDA6500TT/C4,118 |
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9397 750 15057
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 14 June 2005
9 of 37
Philips Semiconductors
TDA6500; TDA6501
5 V mixer/oscillator and synthesizer for PAL and NTSC standards
7.2.2 Read mode
Data can be read from the device by setting the R/W bit to logic 1. The data read format is
shown in Table 11. After the slave address has been recognized, the device generates an
acknowledge pulse and the rst data byte (status byte) is transferred on the SDA line with
the MSB rst. Data is valid on the SDA line during a HIGH-level of the SCL clock signal.
A second data byte can be read from the device if the microcontroller generates an
acknowledge on the SDA line (master acknowledge). End of transmission will occur if no
master acknowledge occurs. The device will then release the data line to allow the
microcontroller to generate a STOP condition.
The POR ag is set to logic 1 at power-on. The ag is reset when an end-of-data is
detected by the device (end of a read sequence).
Control of the loop is made possible with the in-lock ag (FL) which indicates when the
loop is locked (FL = 1).
The internal AGC status is available from the AGC bit. AGC = 1 indicates when the
selected take-over point is reached.
A built-in ADC is available on the P6/ADC pin. The ADC can be used to apply AFC
information to the microcontroller from the IF section of the tuner. The relationship
between the voltage applied to the ADC input and the A2, A1 and A0 bits is given in
[1]
MSB is transmitted rst.
Table 11:
Read data format
Name
Byte
Bit
Ack
MSB [1]
LSB
Address byte
ADB
1
1000MA1
MA0
R/W=1 A
Status byte
SB
POR
FL
1
AGC
A2
A1
A0
-
Table 12:
Description of bits shown in Table 11
Symbol
Description
A
acknowledge
MA1 and MA0
programmable address bits; see Table 7
R/W
logic 1 for read mode
POR
power-on reset ag
POR = 0, normal operation
POR = 1, power-on state
FL
in-lock ag
FL = 0, not locked
FL = 1, the PLL is locked
AGC
internal AGC ag
AGC = 0, internal AGC not active
AGC = 1, internal AGC is active; level below 3 V
A2, A1 and A0
digital output of the 5-level ADC; see Table 13
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