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參數(shù)資料
| 型號(hào)： | TDA5155X |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads |
| 中文描述： | 10 CHANNEL READ WRITE AMPLIFIER CIRCUIT, UUC68 |
| 文件頁(yè)數(shù)： | 13/24頁(yè) |
| 文件大小： | 112K |
| 代理商： | TDA5155X |
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1997 Apr 08
13
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5155
Notes
1.
Unused bits in the registers (indicated by X) are don’t care. Default data, initialized at Power-up, is zero in all
registers. For V
CC
<2.5 V, the register contents are not guaranteed.
V
th
programming uses both the test mode register and the compensation capacitor register. d0 in the formula above
is the LSB of the test mode register and d2 is the d2 data bit of the compensation capacitor register.
2.
0
X
X
X
0
0
1
1
MR current DAC register:
mA
0
X
X
X
0
1
0
0
write current DAC register:
ext
mA
0
X
X
X
0
1
0
1
servo write register:
(d0,d1) = (0,0): one head
(d0,d1) = (1,1): all heads
(d0,d1) = (1,0): odd numbered heads (H1, H3, H5, H7 and H9)
(d0,d1) = (0,1): even numbered heads (H0, H2, H4, H6 and H8)
test mode register:
(d2,d1,d0) = (0,0,0) = not in test mode
(d2,d1,d0) = (0,0,1) = read head test (I
MR1
= I
MR2
)
(d2,d1,d0) = (0,1,0) = read head test (I
MR2
= 5 mA fixed)
(d2,d1,d0) = (0,1,1) = temperature monitor
(d2,d1,d0) = (1,X,d0) = thermal asperity detection, see note 2
V
th
= (210 + 560.d0 + 280.d2)
μ
V
compensation capacitor register:
equivalent differential capacitance = (4.d2 + 2.d1 + 1.d0)
×
2 pF
high frequency gain attenuator register
0
X
X
X
0
1
1
0
0
X
X
X
0
1
1
1
0
X
X
X
1
0
0
0
nominal pole frequency =
0
X
X
X
1
0
0
1
high frequency gain boost register
nominal zero frequency =
0
X
X
X
1
0
1
0
settle time register
settle time:
1
X
X
X
1
1
1
1
device ID register
ID = 8.d3 + 4.d2 + 2.d1 + 1.d0; d3 to d0 are preset to (0,0,1,1)
when a7 = 1, data from the register with address a3 to a0 is read out on
SDATA
1
X
X
X
a3
a2
a1
a0
ADDRESS REGISTERS
(1)
FUNCTION
A7 A6 A5 A4 A3 A2 A1 A0
I
MR
0.5
R
ext
10k
16.d4
8.d3
4.d2
2.d1
d0
+
+
+
+
+
(
)
×
=
I
WR
R
16.d4
8.d3
4.d2
2.d1
d0
+
+
+
+
+
(
)
=
4.d2
8.d3
2.d1
1.d0
+
+
+
---------------------800 MHz
2.d1
1.d0
+
+
+
8.d3
t
st
2
μ
s
4.d2
2.d1
1.d0
1
+
+
+
(
)
------------------------------1
μ
s
+
=
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