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參數(shù)資料
| 型號： | TDA5155X |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads |
| 中文描述： | 10 CHANNEL READ WRITE AMPLIFIER CIRCUIT, UUC68 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 112K |
| 代理商： | TDA5155X |
1997 Apr 08
12
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5155
8.7.5.3
Thermal asperity detector
d2 = logic 1, d1 = x, d0 = (0,1). Unlike the above tests, the
thermal asperity detection does not use the RDx and RDy
outputs. Thus, the reader is fully operational. In case a
thermal asperity is detected, it is flagged at the HUS pin.
The threshold voltage for the thermal asperity detection is
2-bit programmable. These 2 bits consist of d0 (LSB) of
the test mode register (address = 0xxx0110), and d2 of the
compensation capacitor register (address = 0xxx0111).
d0 of test mode register;
d2 of the compensation capacitor register.
8.7.6
W
RITE AMPLIFIER PROGRAMMABLE CAPACITORS
By default (d2 = d1 = d0 = logic 0) the programmable
capacitors are zero. These capacitors are used to improve
the performance of the write amplifier according to the
write amplifier output load.
8.7.7
H
IGH FREQUENCY GAIN ATTENUATOR REGISTER
By default (d3 = d2 = d1 = d0 = logic 0) the high frequency
gain attenuator is not active. The gain attenuator provides
a pole which limits the bandwidth and reduces the high
V
th
210
560.d0
280.d2
+
+
(
) μ
V
=
frequency noise. The HF pole can be used in combination
with the HF zero in order to boost the HF gain locally and
yet limit the very high frequency noise enhancement.
8.7.8
H
IGH FREQUENCY GAIN BOOST REGISTER
By default (d3 = d2 = d1 = d0 = logic 0) the high frequency
gain boost is not active.
The gain boost provides a zero which allows to optimize
the bandwidth of the read amplifier and to correct for
attenuation caused by series inductances in the leads
between the MR heads and the read amplifier inputs.
8.7.9
S
ETTLE PULSE
By default (d2 = d1 = d0 = logic 0) the settle pulse has a
nominal duration of 3
μ
s. Its value can be programmed
from 2.125
μ
s to 3
μ
s according to the following formula:
4.d2
2.d1
1.d0
+
+
(
The settle pulse is used to shorten the transients during
switching.
t
st
2
μ
s
1
+
)
------------------------------1
μ
s
+
=
8.7.10
A
DDRESS REGISTERS SUMMARY
ADDRESS REGISTERS
(1)
FUNCTION
A7 A6 A5 A4 A3 A2 A1 A0
0
X
X
X
0
0
0
0
configuration register:
d0 = 0: use data flip-flop; d0 = 1: by-pass data flip-flop
d1 = 0: WDI PECL; d1 = 1: current input
d2 = 0: write current inhibit active; d2 = 1: write current inhibit inactive
read mode: d3 = 0: HUS active; d3 = 1: HUS HIGH
write mode: d3 = 0: HUS active; d3 = 1: HUS LOW
d4 = 0: read gain nominal; d3 = 1: read gain +3 dB
d5 = 0: read amplifier OFF during write mode; d5 = 1: read amplifier ON
during write mode
power control register:
(d1,d0) = (0,0): sleep mode
(d1,d0) = (1,0) or (0,1): standby mode
(d1,d0) = (1,1): active mode (write or read)
head select register:
(d3,d2,d1,d0) = (0,0,0,0) to (1,0,0,1): H0 to H9
addressing H10 to H15 causes HUS to go HIGH if in write mode and H0 to be
selected if in read mode
0
X
X
X
0
0
0
1
0
X
X
X
0
0
1
0
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