參數(shù)資料
型號: TDA19977BHV/15/C1
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, SOT612-3, HLQFP-144
文件頁數(shù): 12/40頁
文件大?。?/td> 181K
代理商: TDA19977BHV/15/C1
TDA19977A_TDA19977B_1
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 7 August 2008
2 of 40
NXP Semiconductors
TDA19977A; TDA19977B
Triple input HDMI receiver interface with digital processing
on the ITU-R BT.656 format. The device can adjust the output timing of the video port by
altering the values of tsu(Q) and th(Q). In addition, all settings are controllable using the
I2C-bus.
2.
Features
I Complies with the HDMI 1.3a, DVI 1.0, CEA-861-D and HDCP (TDA19977A only)
1.2 standards
I Three independent HDMI inputs, up to the HDMI frequency of 235 MHz
I Embedded auto-adaptive equalizer on all HDMI links
I EDID memory: 253 shared bytes and three bytes dedicated to each HDMI input
I Supports color depth processing (8-bit, 10-bit or 12-bit per color)
I Color gamut metadata packet with interrupt on each update, readable via the I2C-bus
I Up to four S/PDIF or I2S-bus outputs (eight channels) at a sampling rate up to 192 kHz
with IEC 60958/IEC 61937 stream
I HBR audio stream up to 768 kHz with four demultiplexed S/PDIF or I2S-bus outputs
I HBR streams (e.g. DTS-HD master audio and Dolby TrueHD up to eight channels due
to HBR packet for stream with a frame rate up to 768 kHz) support
I DSD and DST audio stream up to six DSD channels output for SACD with DST audio
packet support
I Channel status decoder supports multi-channel reception
I Improved audio clock generation using an external reference clock
I System/master clock output (128/256/512 × fs) enables the use of the UDA1334BTS
I The HDMI interface supports:
N All HDTV formats up to 1920 × 1080p at 50/60 Hz and WUXGA (1920 × 1200p at
60 Hz) with support for reduced blanking
N PC formats up to UXGA (1600 × 1200p at 60 Hz)
I Embedded oscillator (an external crystal can be used)
I Frame and eld detection for interlaced video signal
I Sync timing measurements for format recognition
I Improved system for measurements of blanking and video active area allowing an
accurate recognition of PC and TV formats
I HDCP (TDA19977A only) with repeater capability
I Embedded non-volatile memory storage of HDCP (TDA19977A only) keys
I Programmable color space input signal conversion from RGB-to-YCbCr or
YCbCr-to-RGB
I Output formats: RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2 semi-planar based on the
ITU-R BT.601 standard and YCbCr 4:2:2 ITU-R BT.656
I 8-bit, 10-bit or 12-bit output formats selectable using the I2C-bus (8-bit and 10-bit only
in 4:4:4 format)
I I2C-bus adjustable timing of video port (tsu(Q) and th(Q))
I Downsampling-by-two with selectable lters on Cb and Cr channels in 4:2:2 mode
I Internal video and audio pattern generator
I Controllable using the I2C-bus; 5 V tolerant and bit rate up to 400 kbit/s
I DDC-bus inputs 5 V tolerant and bit rate up to 400 kbit/s
I LV-TTL outputs
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