參數(shù)資料
型號(hào)： TCS59SM704AFTL-75
廠(chǎng)商： Toshiba Corporation
英文描述： 8M×4Banks×4Bits Synchronous DRAM(4組8M×4位同步動(dòng)態(tài)RAM)
中文描述： 8米× 4Banks × 4Bits同步DRAM（4組8米× 4位同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 7/49頁(yè)
文件大?。?/td> 2421K
代理商： TCS59SM704AFTL-75
TC59SM716/08/04AFT/AFTL-70,-75,-80
2000-02-08 7/49
NOTES:
(1)
Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent
damage to the device.
(2)
All voltages are referenced to V
SS
.
(3)
These parameters depend on the cycle rate and these values are measured at a cycle rate with the
minimum values of t
CK
and t
RC
. Input signals are changed one time during t
CK
.
(4)
These parameters depend on the output loading. Specified values are obtained with the output open.
(5)
Power-up sequence is described in Note 11.
(6)
AC TEST CONDITIONS
Output Reference Level
1.4 V, 1.4 V
Output Load
See diagram B below
Input Signal Levels
2.4 V, 0.4 V
Transition Time (rise and fall) of Input Signals
2 ns
Input Reference Level
1.4 V
(7)
Transition times are measured between V
IH
and V
IL
. Transition (rise and fall) of input signals have a
fixed slope.
(8)
t
HZ
defines the time at which the outputs achieve the open circuit condition and is not referenced to
output voltage levels.
AC test load (A)
Output
3.3 V
870
50 pF
1.2 k
AC test load (B)
Output
1.4 V
50 pF
50
Z
=
50
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