參數(shù)資料
型號(hào)： TCS59SM704AFTL-75
廠商： Toshiba Corporation
英文描述： 8M×4Banks×4Bits Synchronous DRAM(4組8M×4位同步動(dòng)態(tài)RAM)
中文描述： 8米× 4Banks × 4Bits同步DRAM（4組8米× 4位同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 6/49頁(yè)
文件大?。?/td> 2421K
代理商： TCS59SM704AFTL-75
TC59SM716/08/04AFT/AFTL-70,-75,-80
2000-02-08 6/49
AC CHARACTERISTICS AND OPERATING CONDITIONS
(V
CC
=
3.3 V
±
0.3 V, Ta
=
0°~70°C) (Notes: 5,
6,
7)
-70
-75
-80
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNITS NOTES
t
RC
Ref/Active to Ref/Active Command Period
57
65
68
t
RAS
Active to Precharge Command Period
42
100000
45
100000
48
100000
t
RCD
Active to Read/Write Command Delay Time
15
20
20
ns
t
CCD
Read/Write(a) to Read/Write(b) Command Period
1
1
1
Cycle
t
RP
Precharge to Active Command Period
15
20
20
t
RRD
Active(a) to Active(b) Command Period
15
15
20
9
CL
*
=
2
7.5
10
10
t
WR
Write-Recovery Time
CL
*
=
3
7
7.5
8
CL
*
=
2
7.5
1000
10
1000
10
1000
t
CK
CLK Cycle Time
CL
*
=
3
7
1000
7.5
1000
8
1000
t
CH
CLK High-Level Width
2.5
2.5
3
t
CL
CLK Low-Level Width
2.5
2.5
3
10
CL
*
=
2
5.4
6
6
t
AC
Access Time from CLK
CL
*
=
3
5.4
5.4
6
t
OH
Output Data Hold Time
3
3
3
t
HZ
Output Data High-Impedance Time
3
7
3
7.5
3
8
8
t
LZ
Output Data Low-Impedance Time
0
0
0
t
SB
Power-Down Mode Entry Time
0
7
0
7.5
0
8
t
t
Transition Time of CLK (rise and fall)
0.5
10
0.5
10
0.5
10
t
DS
Data-In Set-up Time
1.5
1.5
2
t
DH
Data-In Hold Time
0.8
0.8
1
t
AS
Address Set-up Time
1.5
1.5
2
t
AH
Address Hold Time
0.8
0.8
1
t
CKS
CKE Set-up Time
1.5
1.5
2
t
CKH
CKE Hold Time
0.8
0.8
1
t
CMS
Command Set-up Time
1.5
1.5
2
t
CMH
Command Hold Time
0.8
0.8
1
ns
t
REF
Refresh Time
64
64
64
ms
t
RSC
Mode Register Set Cycle Time
14
15
16
ns
9
*
CL means
CAS
latency.
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