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參數(shù)資料
| 型號： | TCM38C17IDL |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QComboE FOUR-CHANNEL QUAD PCM COMBO |
| 中文描述： | QComboE四通道的Quad的PCM組合 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大?。?/td> | 314K |
| 代理商： | TCM38C17IDL |
TCM38C17IDL
QCombo
FOUR-CHANNEL (QUAD) PCMCOMBO
SLWS040C – JUNE 1996 – REVISED OCTOBER 1999
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
2
AREF
Analog reference point (mid-supply). This voltage is generated internally at a nominal 2.375 V. An
external decoupling capacitor (0.1
μ
F) should be connected from AREF to AVSS for filtering purposes.
Noninverting analog input to uncommitted transmit operational amplifier for channel 0
0ANLGIN+
6
I
0ANLGIN–
5
I
Inverting analog input to uncommitted transmit operational amplifier for channel 0
1ANLGIN+
12
I
Noninverting analog input to uncommitted transmit operational amplifier for channel 1
1ANLGIN–
11
I
Inverting analog input to uncommitted transmit operational amplifier for channel 1
2ANLGIN+
43
I
Noninverting analog input to uncommitted transmit operational amplifier for channel 2
2ANLGIN–
44
I
Inverting analog input to uncommitted transmit operational amplifier for channel 2
3ANLGIN+
37
I
Noninverting analog input to uncommitted transmit operational amplifier for channel 3
3ANLGIN–
38
I
Inverting analog input to uncommitted transmit operational amplifier for channel 3
A-law and
μ
-law operation select. When ASEL is connected to ground, A-law is selected. When ASEL is
connected to VDD,
μ
-law is selected (digital).
Analog supply voltage, 5 V,
±
5%
Analog ground return for AVDD supply
Digital supply voltage, 5 V,
±
5%
Phase-locked loop supply voltage, 5 V,
±
5%
Phase-locked loop ground return for DVDDPLL supply
ASEL
24
I
AVDD
46
AVSS
3
DVDD
20
DVDDPLL
21
DVSSPLL
23
DVSS
19
Digital ground return for DVDD supply
0FS
31
I
Frame synchronization clock input/time slot enable for channel 0 TX and RX (digital)
1FS
30
I
Frame synchronization clock input/time slot enable for channel 1 TX and RX (digital)
2FS
29
I
Frame synchronization clock input/time slot enable for channel 2 TX and RX (digital)
3FS
28
I
Frame synchronization clock input/time slot enable for channel 3 TX and RX (digital)
0GSR
8
I
Receive amplifier gain-set input (channel 0). The ratio of an external voltage divider network connected to
0PWRO– and 0PWRO+ determines the receive amplifier gain. Maximum gain occurs when 0GSR is
connected to 0PWRO–, and minimum gain occurs when it is connected to 0PWRO+ (analog).
1GSR
14
I
Receive amplifier gain-set input (channel 1). The ratio of an external voltage divider network connected to
1PWRO– and 1PWRO+ determines the receive amplifier gain. Maximum gain occurs when 1GSR is
connected to 1PWRO–, and minimum gain occurs when it is connected to 1PWRO+ (analog).
2GSR
41
I
Receive amplifier gain-set input (channel 2). The ratio of an external voltage divider network connected to
2PWRO– and 2PWRO+ determines the receive amplifier gain. Maximum gain occurs when 2GSR is
connected to 2PWRO–, and minimum gain occurs when it is connected to 2PWRO+ (analog).
3GSR
35
I
Receive amplifier gain-set input (channel 3). The ratio of an external voltage divider network connected to
3PWRO– and 3PWRO+ determines the receive amplifier gain. Maximum gain occurs when 3GSR is
connected to 3PWRO–, and minimum gain occurs when it is connected to 3PWRO+ (analog).
0GSX
4
O
Output terminal of internal uncommitted transmit operational amplifier for channel 0 (analog)
1GSX
10
O
Output terminal of internal uncommitted transmit operational amplifier for channel 1 (analog)
2GSX
45
O
Output terminal of internal uncommitted transmit operational amplifier for channel 2 (analog)
3GSX
39
O
Output terminal of internal uncommitted transmit operational amplifier for channel 3 (analog)
MCLK
22
I
Master clock input (2.048 MHz) (digital)
PCMIN
25
I
Transmit PCM input (digital)
PCMOUT
27
O
Transmit PCM output (digital)
0PDN
16
I
Power-down select for channel 0. This channel of the device is inactive with a CMOS low-level input to
0PDN and active with a CMOS high-level input to the terminal (digital).
1PDN
17
I
Power-down select for channel 1. This channel of the device is inactive with a CMOS low-level input to
1PDN and active with a CMOS high-level input to the terminal (digital).
2PDN
32
I
Power-down select for channel 2. This channel of the device is inactive with a CMOS low-level input to
2PDN and active with a CMOS high-level input to the terminal (digital).
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