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參數(shù)資料
| 型號： | TCF6000D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | PERIPHERAL CLAMPING ARRAY |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | PLASTIC, SOP-8 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 93K |
| 代理商： | TCF6000D |
TCF6000
2
MOTOROLA ANALOG IC DEVICE DATA
MAXIMUM RATINGS
(TA = 25
°
C, unless otherwise noted, Note 1.)
Rating
Symbol
Value
Unit
Supply Voltage
VCC
Ii
IIK
TJ
PD
θ
JA
TA
Tstg
6.0
V
Supply Current
300
mA
Clamping Current
±
50
mA
Junction Temperature
150
°
C
Power Dissipation (TA = + 85
°
C)
Thermal Resistance (Junction–Ambient)
400
m/W
100
°
C/W
Operating Ambient Temperature Range
–40 to +85
°
C
Storage Temperature Range
–55 to + 150
°
C
NOTE:
1. Values beyond which damage may occur.
ELECTRICAL CHARACTERISTICS
(TA = 25
°
C, 4.5
≤
VCC
≤
5.5 V, unless otherwise noted.)
Characteristics
Symbol
Min
Max
Unit
Positive Clamping Voltage (Note 2)
(IIK = 10 mA, –40
°
C
≤
TA
≤
+ 85
°
C)
V(IK)
–
VCC + 1.0
V
Positive Peak Clamping Current
IIK(P)
V(IK)
–
20
mA
Negative Peak Clamping Voltage
(IIK = –10 mA, –40
°
C
≤
TA
≤
+ 85
°
C)
–0.3
–
V
Negative Peak Clamping Current
IIK(P)
–20
–
mA
Output Leakage Current
(0 V
≤
Vin
≤
VCC)
(0 V
≤
Vin
≤
VCC, –40
°
C
≤
TA
≤
+ 85
°
C)
IL
ILT
–
–
1.0
5.0
μ
A
Channel Crosstalk (ACT = 20 log IL/IIK)
Quiescent Current (Package)
ACT
IB
100
–
dB
–
2.0
mA
NOTE:
2. The device might not give 100% protection in CMOS applications.
CIRCUIT DESCRIPTION
To ensure the reliable operation of any integrated circuit
based electronics system, care has been taken that voltage
transients do not reach the device I/O pins. Most NMOS,
HMOS and Bipolar integrated circuits are particularly
sensitive to negative voltage peaks which can provoke
latch–up or otherwise disturb the normal functioning of the
circuit, and in extreme cases may destroy the device.
Generally the maximum rating for a negative voltage
transients on integral circuits is –0.3 V over the whole
temperature range. Classical protection units have consisted
of diode/resistor networks as shown in Figures 2a and 2b.
The arrangement in Figure 2a does not, in general, meet
the specification and is therefore inadequate.
The problem with the solution shown if Figure 2b lies
mainly with the high current drain through the biassing
devices R1 and D3. A second problem exists if the input line
carries an analog signal. When Vin is close to the ground
potential, currents arising from leakage and mismatch
between D3 and D2 can be sourced into the input line, thus
disturbing the reading.
(a)
(b)
Figure 2. Classical Protection Circuits
VCC
D1
Vin
Rin
D2
Cin
Gnd
Gnd
μ
C
D3
Vin
Rin
Cin
R1
VCC
D2
μ
C
D1
Figure 3 shows the clamping characteristics which
are common to each of the six cells in the Peripheral
Clamping Array.
As with the classical protection circuits, positive voltage
transients are clamped by means of a fast diode to the V
CC
supply line.
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