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參數(shù)資料
| 型號： | TC90A80N |
| 元件分類： | 信號分離 |
| 英文描述： | Y/C SEPARATOR IC, PDIP28 |
| 封裝： | 0.400 INCH, 1.78 MM PITCH, PLASTIC, SDIP-28 |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 378K |
| 代理商： | TC90A80N |
TC90A80N/F
2002-12-04
17
PLL characteristic
(Ta = 25°C, VDD = 5.00 V, clock input: according to test conditions, I
2C bus: according to test
conditions)
Test Conditions (Remarks)
Characteristics
Symbol
Min
Typ.
Max
Unit
I
2C bus setup DATA1 DATA2 DATA3 DATA4
I
2C bus setup
0 0
Pull-in frequency range
fckN
±100
―
kHz
Clock input : Change input frequency at 0.5 Vp-p.
Test content : Change input frequency with fsc
(3.579545 MHz) as reference and
measure pull-in range for PLL.
I
2C bus setup
0 0
Clock input : Change input amplitude at fsc
(3.579545 MHz).
Test content : Increase input clock amplitude from
0 Vp-p and measure input amplitude
for PLL.
I2C bus setup
0 1
0 0
Clock input : Change input amplitude at 2 fsc
(7.15909 MHz).
Test content : Increase input clock amplitude from
0 Vp-p and measure input amplitude
for PLL.
I
2C bus setup
0 2
0 0
Operating input amplitude 1
Vck
0.3
0.5
2.0
Vp-p
Clock input : Change input amplitude at 4 fsc
(14.31818 MHz).
Test content : Increase input clock amplitude from
0 Vp-p and measure input amplitude
for PLL.
I
2C bus setup
0 3
0 0
Operating input amplitude 2
Vck8
0.5
1.0
2.0
Vp-p
Input signal : Apply 10-kHz, 1-Vp-p triangular
wave to pin 9.
Clock input : Change input amplitude at 8 fsc
(28.63636 MHz).
Test content : Increase input clock amplitude from
0 Vp-p and measure input amplitude
where pin 25 output stabilizes.
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