參數(shù)資料
型號: TC90A80N
元件分類: 信號分離
英文描述: Y/C SEPARATOR IC, PDIP28
封裝: 0.400 INCH, 1.78 MM PITCH, PLASTIC, SDIP-28
文件頁數(shù): 23/23頁
文件大小: 378K
代理商: TC90A80N
TC90A80N/F
2002-12-04
9
Description of I
2C Bus Control
(1) Function
: Controls input signal and IC functions. (YCS: Y/C-IN → 3 line Y/C separation, NR: Y and C
input independently → YNR, CNR)
(2) Skew
: Controls skew correction. (OFF: normal mode, ON: Corrects skew every 0.2 H.)
(3) C-Delay
: Controls Y/C time. (Switches chroma signal delay time. : Advances chroma signal. +: Delays
chroma signal.)
(4) D-Range
: Controls input/output gain. (2 Vp-p: 1 V input 2 V output, Gain = 6dB, 1 Vp-p: 1 V input 1 V
output, Gain = 0dB)
(5) Input Clock
: Controls clock PLL. (Select input clock.)
(6) CNR Gain
: Controls CNR cyclic coefficient/subtraction gain. (OFF: Stops CNR. 0.75: Maximum effect)
(7) CNR Lim.
: Controls the CNR limiter. (Limiter level when converting 100 IRE input.: 4 ≈ 31dB to 18 ≈
18dB)
(8) CNR Corr.
: Controls CNR correlation/non-correlation
ON: Controls CNR correlation/non-correlation. → Low vertical color misalignment
OFF: Maximum → effect with vertical color misalignment
(9) Mode1
: Controls parallel output. (Low: Drives out voltage approx. VSS. High: Drives out voltage approx.
VDD.)
(10) Y-EQ fo
: Corrects Y frequency characteristic and controls Y-NC bottom frequency. (high: 4/3 fsc, low: fsc)
(11) Y-EQ Gain
: Controls Y frequency characteristic correction addition gain. (OFF: Stops frequency characteristic
correction. 0.5: Corrects by +3dB at 3 MHz.)
(12) Y-EQ/N.C Lim
: Controls Y frequency characteristic correction coring level and Y-NC limiter. (OFF: N.C OFF,
H*: Limiter level when Y-EQ fo = high, L*: Limiter level when Y-EQ fo = low, When converting
100 IRE input, limiter levels are as follows.2: 37dB, 4: 31dB, 8: 25dB, 14: 20dB)
(13) YNR Corr.
: Controls YNR correlation/non-correlation
ON: Controls YNR correlation/non-correlation → Low Y vertical color misalignment
OFF: Maximum effect → with Y vertical color misalignment
(14) Pulse Middle/High
: Controls High pulse input polarity. (PV: PV with M/H and Killer with Middle/Low, Killer: Killer
with M/H and PV with M/L)
PV: Used for vertical-masking PLL for detecting skew and driving out HD + PV when
compensating skew.
Killer: Used for controlling separation Off, V-Emph Off in YCS Mode, and YNR/CNR Off in NR
Mode.
(15) Sync Out
: Controls pulse output in Skew Correction Mode. (HD: Drives out HD which is synchronous with
output signal. HD + PV: Mixes PV in HD which is synchronous with to output signal.) HD lock
phase is not held (varies from 500 ns to 600 ns).
In modes other than Skew Correction, drives out input C.SYN after delaying approx. 560 ns.
(16) Y/C Mix
: Controls Y/C mix output. (OFF: Drives out separated Y and C. ON: Drives out mixed Y and C
from the Y output pin. The C output pin is mute.)
(17) V-Emph Gain (YCS) : Controls vertical enhancer gain. (OFF: Enhancer Off. +1.5: Maximum effect)
(18) V-Emph N.L (YCS)
: Controls vertical enhancer non-linear point. (4: Low effect, 32: Maximum effect)
(19) V-Emph Core (YCS) : Controls vertical enhancer coring. (OFF: Coring Off. 3: Emphasizes non correlation of approx. 15
mV or more.)
(20) YNR Gain (NR)
: Controls YNR cyclic coefficient/subtraction gain. (OFF: Stops YNR. 0.875: Maximum effect)
(21) YNR Lim (NR)
: Controls the YNR limiter. (Limiter level when converting 100 IRE input.: 1 ≈ 43dB~15 ≈
19dB)
(22) YNR Mode (NR)
: Controls YNR and Y-COMB bandwidths. (*-W: Wideband, *-N: Narrowband)
(Note that the controls of DATA4 D7 to DATA4 D0 vary according to the setting of DATA1 D7 (function).)
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