參數(shù)資料
型號(hào)： TC850CPL
廠商： TelCom Semiconductor, Inc.
英文描述： 15-BIT, FAST-INTEGRATING CMOS ANALOG-TO-DIGITAL CONVERTER
中文描述： 15位，快速整合過(guò)程CMOS模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 6/14頁(yè)
文件大小： 164K
代理商： TC850CPL
3-82
TELCOM SEMICONDUCTOR, INC.
15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
TC850
Figure 2A. Dual-Slope ADC Cycle
Figure 2B. "Fast-Slow" Reference Deintegrate Cycle
additional 6 bits of resolution. The result is 15 bits of
resolution achieved with only 2
9
+ 2
6
(512 + 64, or 576) clock
pulses for deintegration. A complete conversion cycle occu-
pies only 1280 clock pulses.
In order to generate "fast-slow" integration phases, two
voltage references are required. The primary reference
(V
REF1
) is set to one-half of the full-scale voltage (typically
V
REF1
= 1.6384V, and V
FS
= 3.2768V). The secondary
voltage reference (V
REF2
) is set to V
REF1
/64 (typically 25.6
mV). To maintain 15-bit linearity, a tolerance of 0.5% for
V
REF2
is recommended.
ANALOG SECTION DESCRIPTION
The TC850 analog section consists of an input buffer
amplifier, integrator amplifier, comparator, and analog
switches. A simplified block diagram is shown in Figure 3.
Conversion Timing
Each conversion consists of three phases: (1) Zero
Integrator, (2) Signal Integrate, and (3) Reference Integrate
(or Deintegrate). Each conversion cycle requires 1280 inter-
nal clock cycles (Figure 4).
Figure 3. Analog Section Simplified Schematic
AUTO
ZERO
0V
INTEGRATOR
OUTPUT
END OF
CONVERSION
REFERENCE
DEINTEGRATE
SIGNAL
INTEGRATE
TIME
AUTO
ZERO
0V
INTEGRATOR
OUTPUT
END OF
CONVERSION
"SLOW" REFERENCE
DEINTEGRATE
(6-BIT RESOLUTION)
"FAST" REFERENCE
DEINTEGRATE
(9-BIT RESOLUTION)
SIGNAL
INTERGRATE
TIME
CREF1
+
REF1
REF1–
RINT
INTIN
INTOUT
CINT
INT
INT
INT
BUFFER*
BUFF
INTEGRATOR*
COMPARATOR*
TO
DIGITAL
SECTION
DE1
(+)
DE
DE
DE
Z1
DE
DE1
(+)
DE1
(–)
DE1
(–)
DE2
(+)
DE2
(–)
DE1
(+)
DE1
(–)
COMMON
C+
C–
C–
C–
CREF2
REF2+
IN+
IN–
+
–
+
–
+
–
TC850
*AUTO-ZEROED
AMPLIFIERS
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