參數(shù)資料
型號: TC850CPL
廠商: TelCom Semiconductor, Inc.
英文描述: 15-BIT, FAST-INTEGRATING CMOS ANALOG-TO-DIGITAL CONVERTER
中文描述: 15位,快速整合過程CMOS模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 3/14頁
文件大小: 164K
代理商: TC850CPL
3-79
TELCOM SEMICONDUCTOR, INC.
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ELECTRICAL CHARACTERISTICS
(Cont.)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
t
LH
Low/High Byte Access Time
Clock Setup Time
RD Minimum Pulse Width
RD Minimum Delay Time
WR Minimum Pulse Width
Clock Setup Time
CS = HIGH, CE = LOW, RD = LOW (Note 1)
Positive or Negative Pulse Width
CS = HIGH, CE = LOW (Note 2)
CS = HIGH, CE = LOW (Note 2)
CS = HIGH, CE = LOW, Demand Mode
Positive or Negative Pulse Width
100
450
150
75
100
140
230
50
25
300
nsec
nsec
nsec
nsec
nsec
nsec
t
WRE
t
WRD
t
WWR
NOTES:
1. Demand mode, CONT/DEMAND = LOW. Figure 10 timing diagram. C
L
= 100pF.
2. Continuous mode, CONT/DEMAND = HIGH. Figure 12 timing diagram.
3. Digital inputs have CMOS logic levels and internal pull-up/pull-down resistors. For TTL compatibility, external pull-up resistors to V
CC
are
recommended.
TC850CPL
TC850IJL
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33
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25
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21
COMMON
CBUFB
BUFFER
INTIN
INTOUT
VSS
COMP
NC = NO INTERNAL CONNECTION
GND
CINTA
CBUFA
CINTB
IN–
IN+
REF –
TEST
OSC2
OSC1
BUSY
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
L/H
OVR/POL
CONT/DEMAND
RD
CE
CS
WR
VDD
REF1
+
+
REF2
CREF1
CREF1
CREF2
+
COMMON
I
I
C
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37
38
39
13
10
9
8
7
18
B
19
O
20
21
T
23
24
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5
4
3
1
44
2
22
43
42
41
40
25
26
27
28
32
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31
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30
16
29
17
11
12
TC850CLW
TC850ILW
CBUFB
CINTA
CBUFA
CINTB
IN–
NC
N
N
IN+
R
G
O
DB0
DB1
DB2
DB3
DB4
NC
DB5
DB6
DB7
C
C
W
R
C
OVR/POL
L/H
B
V
V
R
+
REF2
+
C
+
C
+
PIN CONFIGURATIONS
TC850
15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
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