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參數(shù)資料
| 型號： | TC850CLW |
| 廠商： | TelCom Semiconductor, Inc. |
| 英文描述： | 15-BIT, FAST-INTEGRATING CMOS ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 15位，快速整合過程CMOS模擬數(shù)字轉換器 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 164K |
| 代理商： | TC850CLW |
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TELCOM SEMICONDUCTOR, INC.
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Digital Operating Modes
Two modes of operation are available with the TC850,
continuous conversions and on-demand. The operating
mode is controlled by the CONT/DEMAND input. The bus
interface method is different for continuous and demand
modes of operation.
Demand Mode Operation
When CONT/DEMAND is low, the TC850 performs one
conversion each time the chip is selected and the WR input
is pulsed low. Data is valid on the falling edge of the BUSY
output and can be accessed using the interface truth table
(Table 1).
Continuous Mode Operation
When CONT/DEMAND is high, the TC850 continuously
performs conversions. Data will be valid on the falling edge
of the BUSY output, and remains valid for 443-1/2 clock
cycles.
The low/high (L/H) byte-select and overrange/polarity
(OVR/POL) inputs are disabled during continuous mode
operation. Data must be read in three consecutive bytes, as
shown in Table I.
NOTE:
In continuous mode, the conversion result must be read within 443-
1/2 clock cycles of the BUSY output falling edge. After this time (i.e., 1/2
clock cycle before BUSY goes high) the internal counters are reset and the
data is lost.
Table 1. Bus Interface Truth Table
CECS
RD
CONT/DEMAND
L/H
OVR/POL
DB7
DB6–DB0
Pins 1 and 2
0
0
Pin 4
0
0
Pin 5
0
0
Pin 7
0
0
Pin 6
0
1
Pin 8
Pin 9-Pin 15 (Note 1)
Data Bits 14 – 8
Data Bits 14 – 8
"1" = Input Positive
"1" = Input Overrange
(Note 2)
Data Bit 7
Note 3
High-Impedance State
High-Impedance State
0
0
0
1
0
0
1
X
0
1
X
X
1
X
X
X
X
X
X
X
Data Bits 6 – 0
NOTES:
1. Pin numbers refer to 40-pin DIP.
2. Extended overrange operation: Although rated at 15 bits (
±
32,767 counts) of resolution, the TC850 provides an additional 191 counts
above full scale. For example, with a full-scale input of 3.2768V, the maximum analog input voltage which will be properly converted is
3.2958V. The extended resolution is signified by the overrange bit being high and the low-order byte contents being between 0 and 190.
For example, with a full-scale voltage of 3.2768V:
V
IN
Overrange Bit
Low Byte
3.2767V
Low
255
10
3.2768V
High
000
10
3.2769V
High
001
10
3.2867V
High
099
10
3. Continuous mode data transfer:
a. In continuous mode, data MUST be read in three sequential bytes after the BUSY output goes low:
(1) The first byte read will be the high-order byte, with DB7 = polarity.
(2) The second byte read will contain the low-order byte.
(3) The third byte read will again be the high-order byte, but with DB7 = overrange.
b. All three data bytes must be read within 443-1/2 clock cycles after the falling edge of BUSY.
c. The RD input must go high after each byte is read, so that the internal byte counter will be incremented. However, the CS and CE
inputs can remain enabled through the entire data transfer sequence.
Data Bits 14–8
127
10
0
10
0
10
0
10
TC850
15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
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