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參數(shù)資料
| 型號： | TC850CLW |
| 廠商： | TelCom Semiconductor, Inc. |
| 英文描述： | 15-BIT, FAST-INTEGRATING CMOS ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 15位，快速整合過程CMOS模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 164K |
| 代理商： | TC850CLW |
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TELCOM SEMICONDUCTOR, INC.
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During the slow deintegrate phase, the internal V
IN
node is now connected to the C
REF2
capacitor, and the
residual charge on the integrator capacitor is further dis-
charged a maximum of 64 clock pulses. At this point, the
analog input voltage has been converted with 15 bits of
resolution.
If the analog input is greater than full scale, the TC850
performs up to three overrange deintegrate subphases.
Each subphase occupies a maximum of 64 clock pulses.
The overrange feature permits analog inputs up to 192 LSBs
greater than full scale to be correctly converted. This feature
permits the user to digitally null up to 192 counts of input
offset, while retaining full 15-bit resolution.
In addition to 512 counts of fast, 64 counts of slow, and
192 counts of overrange deintegrate, the reference-inte-
grate phase uses 10 clock pulses to permit internal nodes to
settle. Therefore, the reference integrate cycle occupies 778
clock pulses.
+
Pin Description (Analog)
Differential Inputs (IN
+
and IN
–
)
The analog signal to be measured is applied at the IN
+
and IN
–
inputs. The differential input voltage must be within
the common-mode range of the converter. The input com-
mon-mode range extends from V
DD
–1.5V to V
SS
+1.5V.
Within this common-mode voltage range, an 86 dB CMRR
is typical.
The integrator output also follows the common-mode
voltage. The integrator output must not be allowed to satu-
rate. A worst-case condition exists, for example, when a
large, positive common-mode voltage with a near full-scale
negative differential input voltage is applied. The negative
input signal drives the integrator positive when most of its
available swing has been used up by the positive common-
mode voltage. For applications where maximum common-
mode range is critical, integrator swing can be reduced. The
integrator output can swing within 0.4V of either supply
without loss of linearity.
Reference-Integrate Phase
During reference-integrate phase, the charge stored on
the integrator capacitor is discharged. The time required to
discharge the capacitor is proportional to the analog input
voltage.
The reference integrate phase is divided into three
subphases: (1) fast, (2) slow, and (3) overrange deintegrate.
During fast deintegrate, V
IN
analog common and V
IN
charged reference capacitor (C
REF1
). The integrator capaci-
tor is rapidly discharged for a maximum of 512 internal clock
pulses, yielding 9 bits of resolution.
–
is internally connected to
+
is connected across the previously-
t
SI
= 4
×
256
f
OSC
Figure 4. Conversion Timing
Zero-Integrator Phase
During the zero-integrator phase, the differential input
signal is disconnected from the circuit by opening internal
analog gates. The internal nodes are shorted to analog
common (ground) to establish a zero-input condition. At the
same time, a feedback loop is closed around the input buffer,
integrator, and comparator. The feedback loop ensures the
integrator output is near 0V before the signal-integrate
phase begins.
During this phase, a chopper-stabilization technique is
used to cancel offset errors in the input buffer, integrator,
and comparator. Error voltages are stored on the C
BUFF
,
C
INT
, and COMP capacitors. The zero-integrate phase
requires 246 clock cycles.
Signal-Integrate Phase
The zero-integrator loop is opened and the internal
differential inputs are connected to IN
+
and IN
–
. The differ-
ential input signal is integrated for a fixed time period. The
TC850 signal-integrate period is 256 clock periods, or counts.
The crystal oscillator frequency is
4
4 before clocking the
internal counters.
The integration time period is:
CONVERSION
PHASE
INTERNAL
CLOCK
SIGNAL
INTEGRATE
ZERO INTEGRATOR
REFERENCE INTEGRATE
1280 CLOCK CYCLES
. .
246
256
778
. . . . . . .
. . . . . . . . . . . .
TC850
15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
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