參數(shù)資料
型號: TC820C/KW
元件分類: ADC
英文描述: 1-CH 3-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PQFP44
封裝: 10 X 10 MM, 2 MM HEIGHT, PLASTIC, MQFP-44
文件頁數(shù): 34/34頁
文件大?。?/td> 435K
代理商: TC820C/KW
2007 Microchip Technology Inc.
DS21476C-page 9
TC820
In a simple dual slope converter, a complete conver-
sion requires the integrator output to "ramp-up" from
zero and "ramp-down" back to zero. A simple mathe-
matical equation relates the input signal, reference
voltage, and integration time.
EQUATION 3-1:
For a constant VINT:
EQUATION 3-2:
FIGURE 3-1:
Basic Dual Slope Converter.
Accuracy in a dual slope converter is unrelated to the
integrating resistor and capacitor values as long as
they are stable during a measurement cycle. An
inherent benefit of the dual slope technique is noise
immunity. Noise spikes are integrated or averaged to
zero during the integration periods, making integrating
ADCs immune to the large conversion errors that
plague successive approximation converters in high
noise environments. Interfering signals, with frequency
components at multiples of the averaging (integrating)
period, will be attenuated (Figure 3-2). Integrating
ADCs commonly operate with the signal integration
period set to a multiple of the 50/60Hz power line
period.
FIGURE 3-2:
Normal Mode Rejection of
Dual Slope Converter.
3.2
Analog Section
In addition to the basic integrate and de-integrate dual
slope phases discussed above, the TC820 design
incorporates a "zero integrator output" phase and an
"auto-zero" phase. These additional phases ensure
that the integrator starts at 0V (even after a severe over
range conversion), and that all offset voltage errors
(buffer amplifier, integrator and comparator) are
removed from the conversion. A true digital zero
reading is assured without any external adjustments.
A complete conversion consists of four distinct phases:
1.
Zero Integrator Output.
2.
Auto-Zero.
3.
Signal Integrate.
4.
Reference De-integrate.
3.2.1
ZERO INTEGRATOR OUTPUT
PHASE
This phase guarantees that the integrator output is at
0V before the system zero phase is entered, ensuring
that the true system offset voltages will be compen-
sated for even after an over range conversion. The
duration of this phase is 500 counts plus the unused
de-integrate counts.
3.2.2
AUTO-ZERO PHASE
During the auto-zero phase, the differential input signal
is disconnected from the measurement circuit by
opening internal analog switches, and the internal
nodes are shorted to Analog Common (0VREF) to
establish a zero input condition. Additional analog
switches close a feedback loop around the integrator
and comparator to permit comparator offset voltage
error compensation. A voltage established on CAZ then
compensates for internal device offset voltages during
the measurement cycle. The auto-zero phase residual
is typically 10 V to 15 mV. The auto-zero duration is
1500 counts.
1
RINTCINT
tINT
0
VIN(t)dt =
VREFtDEINT
RINTCINT
Where: VREF = Reference Voltage
tINT
= Integration Time
tDEINT = De-integration Time
VIN = VREF
tDEINT
tINT
+
REF
Voltage
Analog
Input Signal
+
Display
Switch
Driver
Control
Logioc
Integrator
Output
Clock
Counter
Polarity Control
Phase
Control
VIN = VREF
VIN = 1.2VREF
Variable Reference
Integrate Time
Fixed Signal
Integrate Time
Integrator
C
Comparator
R
30
20
10
0
0.1/T
1/T
10/T
Input Frequency
Normal
Mode
Rejection
(dB)
T = Measurement
Period
相關(guān)PDF資料
PDF描述
TC820CKWTR 1-CH DUAL-SLOPE ADC, PQFP44
TC820CLWTR 1-CH DUAL-SLOPE ADC, PQCC44
TC820CKW 1-CH DUAL-SLOPE ADC, PQFP44
TC820CLW 1-CH DUAL-SLOPE ADC, PQCC44
TC820CPL 1-CH DUAL-SLOPE ADC, PDIP40
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