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參數(shù)資料
| 型號(hào)： | TC8129CKW |
| 元件分類： | ADC |
| 英文描述： | 1-CH PROPRIETARY METHOD ADC, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 137K |
| 代理商： | TC8129CKW |
10
TC8129
4C\VDigit Auto-Ranging DMM ADC
TC8129 - 3/29/96-2
2001 Microchip Technology Inc.
DS21473A
READ Timing
RD
SCLK
DATA
tRDS
tRD
tDCK
tPWH
tPWL
LOAD Timing
LD
SCLK
DATA
tLDS
tDH
tDS
Figure 6. TC8129 Input/Output Timing Specifications
FUNCTION AND RANGE COMMANDS
The TC8129’s operation is controlled by the TC8131 or
by an external microcomputer. Measurement functions and
ranges are set by sending a 12-bit serial word to the
TC8129. The serial word is shifted into a register in the
TC8129. At the end of each conversion, the contents of the
register are decoded to set the function and range.
The format for sending commands to the TC8129 is
shown in Figure 7. Data bits are sent to the TC8129 in B0,
B1,..., B11 order (i.e. B0 is the first bit clocked into the
TC8129).
SCLK
R10
DATA
P00
TC8129
Pin
LD
R11
TC8131
Pin
B0 B1 B2
B11 B12
(Pin 41)
(Pin 37)
(Pin 40)
(Pin 48)
(Pin 52)
(Pin 47)
Figure 5. TC8131 to TC8129 Serial Data Transfer
Serial Clock (SCLK, Pin 40)
The SCLK input is used to control data transfer to and
from the TC8129. The SCLK input is completely asynchro-
nous, which simplifies the interface to a wide variety of
single-chip microcomputers.
Measurement mode and range commands are entered
into the TC8129 (when LD is LOW) and A/D conversion
data is read from the TC8129 (when RD is LOW) by pulsing
the SCLK input. Data must be stable on the rising edge of
SCLK when LD is LOW. New data is available on the falling
edge of SCLK when RD is LOW.
Data Input/Output (DATA, Pin 37)
Commands and A/D results are transferred via the
DATA pin. This pin provides bidirectional, 3-state I/O. The
DATA pin’s function is controlled by the RD and LD inputs.
When RD is LOW, the DATA pin is an output for the A/D
converter results. When LD is LOW, DATA is a high imped-
ance input for measurement and range commands.
Data Interface Timing
The TC8129 input and output timing specifications are
contained in Table 1 and timing diagrams are shown in
Figure 6. The serial data interface is static, so that a
microcomputer or other logic only needs to meet the mini-
mum setup times to ensure correct operation. No critical
timing patterns are required to read data from or write data
to the TC8129.
Table 1. TC8129 Input/Output Timing Specifications
Parameter
Symbol
Min
Units
RD Delay Time
tRD
250
nsec
Data RD Setup Time
tRDS
1
sec
SCLK to DOUT Delay
tDCK
500
nsec
LD Setup Time
tLDS
1
sec
Data LD Setup Time
tDS
150
nsec
Data LD Hold Time
tDH
100
nsec
SCLK Pulse Width Low
tPWL
200
nsec
SCLK Pulse Width High
tPWH
200
nsec
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