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參數(shù)資料
| 型號(hào)： | TC8129CKW |
| 元件分類： | ADC |
| 英文描述： | 1-CH PROPRIETARY METHOD ADC, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 17/17頁 |
| 文件大小： | 137K |
| 代理商： | TC8129CKW |
9
TC8129
TC8129 - 3/29/96-2
2001 Microchip Technology Inc.
DS21473A
4C\VDigit Auto-Ranging DMM ADC
Protection,
Input
Shaping
and Level
Shifting
(See Typical
Application
Schematic)
TC8129
Frequency
Input
÷10 ÷10
Prescaler
Control
TC8131
Serial
Data
Interface
÷10
fIN
fOUT
K10
DMM
Control
Frequency
Counter
-40
0
-20
10
0
20
+20
30
+40
40
35
25
15
5
°C°F
AC
mVA
kM
Hz
n
F
– +
AUTO
DELTA
HFE
dBm
MAX
ZOOM
MIN
AVG
HOLD
Figure 2. Simplified Block Diagram of the Frequency Counter Prescaler
Frequency
The TC8129 includes a 3-decade prescaler (Figure 2)
which extends frequency measurements to 4MHz. The
prescaler can be programmed to divide by 1, 10, 100 or
1000. The signal to be measured is applied to the TC8129’s
fIN input and comes out on the fOUT output.
The TC8131 contains the frequency counter. Pulses
on the TC8131’s K10 input are counted with a one second
time base, to a maximum of 4kHz. If the input to the
TC8129 exceeds 4kHz, the overrange bit is set, and the
TC8131 selects the TC8129’s next higher prescaler value.
Data Interface
The TC8129 incorporates a 5-line serial interface for
exchanging data with the TC8131 or with a microcomputer
(Figure 3). The TC8131 sends measurement function and
range commands to the TC8129, and the TC8129 sends
A/D conversion results to the TC8131. The serial data
interface reduces pin count and simplifies interfacing to
both low- and high-end microcomputers.
SCLK
R10
DATA
R13
TC8129
LD
R11
RD
R12
DV
K13
TC8131
Figure 3. Serial Data Interface
PIN DESCRIPTIONS, I/O
Data Valid (DV, Pin 35)
The DV output of the TC8129 goes LOW at the end of
each conversion. This output signals the TC8131 that a
new A/D value can be read from the TC8129. When the
TC8129’s RD input is driven LOW to start the data transfer,
DV will go HIGH. DV will also go HIGH if data is not read
within 25 msec.
Read (RD, Pin 38)
The RD input controls data transfer from the TC8129 to
the TC8131 (Figure 4). When RD goes LOW, the TC8129’s
Data output switches to its low impedance state and the
first data bit (the overrange bit) is placed on the DATA pin.
Succeeding output bits are transferred to the DATA pin on
the falling edge of SCLK. RD is held LOW until all data is
clocked out of the TC8129. When RD goes HIGH, the
DATA output will return to its HIGH impedance state.
SCLK
R10
TC8129
Pin
DV
K13
TC8131
Pin
RD
R12
DATA
P00
B0
B1 B2
B39 B40
(Pin 35)
(Pin 38)
(Pin 40)
(Pin 37)
(Pin 63)
(Pin 49)
(Pin 47)
(Pin 52)
Figure 4. TC8129 to TC8131 Serial Data Transfer
Load (LD, Pin 41)
Measurement mode and range commands are clocked
into the TC8129 when the LD input is LOW (Figure 5). Data
must be stable on the rising edge of SCLK.
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