參數(shù)資料
型號: TC7MP3125FK
廠商: Toshiba Corporation
英文描述: Low Voltage/Low Power 2-Bit 】 2 Dual Supply Bus Transceiver
中文描述: 低電壓/低功率2位】2雙電源總線收發(fā)器
文件頁數(shù): 15/23頁
文件大?。?/td> 338K
代理商: TC7MP3125FK
TC7MP3125FK/FTG
2007-10-19
15
V
CCA
=
1.5
±
0.1 V, V
CCB
=
3.3
±
0.3 V
Characteristics
Symbol
Test Condition
Min
Max
Unit
Propagation delay time
(Bn
An)
t
pLH
t
pHL
Figure 1, Figure 2
1.0
10.3
3-state output enable time
(OE
An)
t
pZL
t
pZH
Figure 1, Figure 3
1.0
18.5
3-state output disable time
(
OE
An)
t
pLZ
t
pHZ
Figure 1, Figure 3
1.0
13.0
ns
Propagation delay time
(An
Bn)
t
pLH
t
pHL
Figure 1, Figure 2
1.0
8.6
3-state output enable time
(
OE
Bn)
t
pZL
t
pZH
Figure 1, Figure 3
1.0
14.3
3-state output disable time
(OE
Bn)
t
pLZ
t
pHZ
Figure 1, Figure 3
1.0
6.6
ns
Output to output skew
t
osLH
t
osHL
(Note)
1.5
ns
Note: Parameter guaranteed by design.
(t
osLH
=
|t
pLHm
t
pLHn
|, t
osHL
=
|t
pHLm
t
pHLn
|)
V
CCA
=
1.2
±
0.1 V, V
CCB
=
3.3
±
0.3 V
Characteristics
Symbol
Test Condition
Min
Max
Unit
Propagation delay time
(Bn
An)
t
pLH
t
pHL
Figure 1, Figure 2
1.0
61
3-state output enable time
(OE
An)
t
pZL
t
pZH
Figure 1, Figure 3
1.0
95
3-state output disable time
(OE
An)
t
pLZ
t
pHZ
Figure 1, Figure 3
1.0
44
ns
Propagation delay time
(An
Bn)
t
pLH
t
pHL
Figure 1, Figure 2
1.0
22
3-state output enable time
(OE
Bn)
t
pZL
t
pZH
Figure 1, Figure 3
1.0
52
3-state output disable time
(OE
Bn)
t
pLZ
t
pHZ
Figure 1, Figure 3
1.0
18
ns
Output to output skew
t
osLH
t
osHL
(Note)
1.5
ns
Note: Parameter guaranteed by design.
(t
osLH
=
|t
pLHm
t
pLHn
|, t
osHL
=
|t
pHLm
t
pHLn
|)
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TC7MP3125FK(EL) 制造商:Toshiba America Electronic Components 功能描述:Level shifter 2bx2 dual supply bus US16
TC7MP3125FK(SPL) 制造商:Toshiba America Electronic Components 功能描述:
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TC7MP3125FTG 功能描述:總線收發(fā)器 Bus Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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